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Test resource partitioning for system-on-a-chip

Author: Krishnendu Chakrabarty; Vikram Iyengar; Anshuman Chandra
Publisher: New York : Springer, ©2002.
Series: Frontiers in electronic testing, 20.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Printed edition:
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Krishnendu Chakrabarty; Vikram Iyengar; Anshuman Chandra
ISBN: 9781461511137 1461511135 1461354005 9781461354000
OCLC Number: 847552569
Notes: Softcover reprint of the hardcover 1st edition originally published by Kluwer in 2002.
Description: 1 online resource (xii, 232 pages :) : illustrations.
Contents: 1. Test Resource Partitioning --
2. Test Access Mechanism Optimization --
3. Improved Test Bus Partitioning --
4. Test Wrapper And TAM Co-Optimization --
5. Test Scheduling --
6. Precedence, Preemption, And Power Constraints --
7. Test Data Compression Using Golomb Codes --
8. Frequency-Directed Run-Length (FDR) Codes --
9. TRP for Low-Power Scan Testing --
10. Conclusion --
References.
Series Title: Frontiers in electronic testing, 20.
Responsibility: Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra.

Abstract:

Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic. SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume. Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.

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