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Timing optimization for high-speed digital circuits

Author: I S Kourtev
Publisher: New York ; Berlin : Springer, 2007.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
Details timing analysis and optimization techniques for circuits with level-sensitive memory elements. This book contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling.
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Kourtev, I.S.
Timing optimization for high-speed digital circuits.
New York ; Berlin : Springer, 2007
(OCoLC)124038403
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: I S Kourtev
ISBN: 9780387710563 0387710566
OCLC Number: 310335615
Description: 1 online resource (approximately 300 pages)
Contents: 1 Introduction; 2 VLSI Systems; 2.1 Signal Representation; 2.2 Synchronous VLSI Systems; 2.3 The VLSI Design Process; 2.4 Summary; 3 Signal Delay in VLSI Systems; 3.1 Delay Metrics; 3.2 Devices and Interconnections; 4 Timing Properties of Synchronous Systems; 4.1 StorageElements; 4.2 Latches; 4.3 Parameters of Latches; 4.4 Flip-Flops; 4.5 Parameters of Flip-Flops; 4.6 The Clock Signal; 4.7 Single-Phase Path with Flip-Flops; 4.8 Single-Phase Path with Latches; 4.9 Multi-Phase Path with Latches; 4.10 A Final Note; 5 Clock Skew Scheduling and Clock Tree Synthesis; 5.1 Background. 5.2 Definitions and Graphical Model5.3 Clock Scheduling; 5.4 Timing Constraints and Design Automation; 5.5 Structure of the Clock Distribution Network; 5.6 Solution of the Clock Tree Synthesis Problem; 5.7 Software Implementation; 6 Clock Skew Scheduling of Level-Sensitive Circuits; 6.1 Clock Scheduling for Level-Sensitive Circuits; 6.2 Iterative Approach to Clock Skew Scheduling; 6.3 Linearization of the Timing Analysis; 6.4 An Example and Experimental Results; 6.5 Optimality of the LP Formulation; 6.6 Multi-Phase Level-Sensitive Circuits; 6.7 Summary. 7 Clock Skew Scheduling for Improved Reliability7.1 Problem Formulation; 7.2 Derivation of the QP Algorithm; 8 Delay Insertion and Clock Skew Scheduling; 8.1 Limitations on Minimum Clock Period; 8.2 Delay Insertion Method; 8.3 Linear Problem Formulation; 8.4 Practical Concerns in Modeling and Application; 8.5 Summary; 9 Practical Considerations; 9.1 Computational Analysis; 9.2 Unconstrained Basis Skews; 9.3 I/O Registers and Target Delays; 9.4 Summary; 10 Clock Skew Scheduling in Rotary Clocking Technology; 10.1 Resonant Clocking; 10.2 Physical Design Flow. 10.3 Parallelization of Clock Skew Scheduling10.4 Summary; 11 Experimental Results; 11.1 Clock Skew Scheduling of Level-Sensitive Circuits; 11.2 Multi-Phase Level-Sensitive Circuits; 11.3 Quadratic Programming (QP) for Maximizing Safety; 11.4 Delay Insertion in Clock Skew Scheduling; 11.5 Physical Design of Rotary Clock Synchronized Circuits; 12 Conclusions; References; Index.
Responsibility: I.S. Kourtev, E.G Friedman, B. Tastin.

Abstract:

Details timing analysis and optimization techniques for circuits with level-sensitive memory elements. This book contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling.

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Primary Entity

<http://www.worldcat.org/oclc/310335615> # Timing optimization for high-speed digital circuits
    a schema:CreativeWork, schema:Book, schema:MediaObject ;
    library:oclcnum "310335615" ;
    library:placeOfPublication <http://dbpedia.org/resource/New_York_City> ; # New York
    library:placeOfPublication <http://id.loc.gov/vocabulary/countries/nyu> ;
    library:placeOfPublication <http://experiment.worldcat.org/entity/work/data/102684002#Place/berlin> ; # Berlin
    schema:about <http://experiment.worldcat.org/entity/work/data/102684002#Topic/timing_circuits_design_and_construction> ; # Timing circuits--Design and construction
    schema:about <http://experiment.worldcat.org/entity/work/data/102684002#Topic/synchronization> ; # Synchronization
    schema:about <http://id.loc.gov/authorities/subjects/sh2008104742> ; # Integrated circuits--Very large scale integration--Design and construction
    schema:about <http://dewey.info/class/621.395/e22/> ;
    schema:about <http://experiment.worldcat.org/entity/work/data/102684002#Topic/integrated_circuits_very_large_scale_integration_design_and_construction> ; # Integrated circuits--Very large scale integration--Design and construction
    schema:about <http://experiment.worldcat.org/entity/work/data/102684002#Topic/ingenierie> ; # Ingénierie
    schema:bookFormat schema:EBook ;
    schema:creator <http://viaf.org/viaf/277137709> ; # I. S. Kourtev
    schema:datePublished "2007" ;
    schema:description "Details timing analysis and optimization techniques for circuits with level-sensitive memory elements. This book contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling."@en ;
    schema:description "1 Introduction; 2 VLSI Systems; 2.1 Signal Representation; 2.2 Synchronous VLSI Systems; 2.3 The VLSI Design Process; 2.4 Summary; 3 Signal Delay in VLSI Systems; 3.1 Delay Metrics; 3.2 Devices and Interconnections; 4 Timing Properties of Synchronous Systems; 4.1 StorageElements; 4.2 Latches; 4.3 Parameters of Latches; 4.4 Flip-Flops; 4.5 Parameters of Flip-Flops; 4.6 The Clock Signal; 4.7 Single-Phase Path with Flip-Flops; 4.8 Single-Phase Path with Latches; 4.9 Multi-Phase Path with Latches; 4.10 A Final Note; 5 Clock Skew Scheduling and Clock Tree Synthesis; 5.1 Background."@en ;
    schema:exampleOfWork <http://worldcat.org/entity/work/id/102684002> ;
    schema:genre "Electronic books"@en ;
    schema:inLanguage "en" ;
    schema:isSimilarTo <http://www.worldcat.org/oclc/124038403> ;
    schema:name "Timing optimization for high-speed digital circuits"@en ;
    schema:productID "310335615" ;
    schema:publication <http://www.worldcat.org/title/-/oclc/310335615#PublicationEvent/new_york_berlin_springer_2007> ;
    schema:publisher <http://experiment.worldcat.org/entity/work/data/102684002#Agent/springer> ; # Springer
    schema:url <http://proxy.library.carleton.ca/login?url=http://books.scholarsportal.info/viewdoc.html?id=/ebooks/ebooks0/springer/2009-12-01/8/9780387710563> ;
    schema:url <http://proxy.library.carleton.ca/login?url=http://dx.doi.org/10.1007/978-0-387-71056-3> ;
    schema:url <http://public.eblib.com/choice/publicfullrecord.aspx?p=417163> ;
    schema:url <http://dx.doi.org/10.1007/978-0-387-71056-3> ;
    schema:workExample <http://worldcat.org/isbn/9780387710563> ;
    wdrs:describedby <http://www.worldcat.org/title/-/oclc/310335615> ;
    .


Related Entities

<http://dbpedia.org/resource/New_York_City> # New York
    a schema:Place ;
    schema:name "New York" ;
    .

<http://experiment.worldcat.org/entity/work/data/102684002#Topic/integrated_circuits_very_large_scale_integration_design_and_construction> # Integrated circuits--Very large scale integration--Design and construction
    a schema:Intangible ;
    schema:name "Integrated circuits--Very large scale integration--Design and construction"@en ;
    .

<http://experiment.worldcat.org/entity/work/data/102684002#Topic/timing_circuits_design_and_construction> # Timing circuits--Design and construction
    a schema:Intangible ;
    schema:hasPart <http://id.loc.gov/authorities/subjects/sh85135453> ;
    schema:name "Timing circuits--Design and construction"@en ;
    .

<http://id.loc.gov/authorities/subjects/sh2008104742> # Integrated circuits--Very large scale integration--Design and construction
    a schema:Intangible ;
    schema:name "Integrated circuits--Very large scale integration--Design and construction"@en ;
    .

<http://viaf.org/viaf/277137709> # I. S. Kourtev
    a schema:Person ;
    schema:familyName "Kourtev" ;
    schema:givenName "I. S." ;
    schema:name "I. S. Kourtev" ;
    .

<http://worldcat.org/isbn/9780387710563>
    a schema:ProductModel ;
    schema:isbn "0387710566" ;
    schema:isbn "9780387710563" ;
    .

<http://www.worldcat.org/oclc/124038403>
    a schema:CreativeWork ;
    rdfs:label "Timing optimization for high-speed digital circuits." ;
    schema:description "Print version:" ;
    schema:isSimilarTo <http://www.worldcat.org/oclc/310335615> ; # Timing optimization for high-speed digital circuits
    .


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