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Trace-Based Post-Silicon Validation for VLSI Circuits.

Author: Xiao Liu; Qiang Xu
Publisher: Dordrecht : Springer, 2013.
Series: Lecture notes in electrical engineering.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits. The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective. A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described,  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Liu, Xiao.
Trace-Based Post-Silicon Validation for VLSI Circuits.
Dordrecht : Springer, ©2013
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Xiao Liu; Qiang Xu
ISBN: 9783319005331 3319005332 1299857264 9781299857261 9783319005324 3319005324
OCLC Number: 854975882
Description: 1 online resource (118 pages).
Contents: Preface; Acknowledgments; Contents; 1 Introduction; 1.1 VLSI Design Trends and Validation Challenges; 1.2 Key Contributions and Book Outline; 2 State of the Art on Post-Silicon Validation; 2.1 Trace Signal Selection; 2.2 Interconnection Fabric Design for Trace Data Transfer; 2.3 Trace Data Compression; 2.4 Trace-Based Debug Control; 3 Signal Selection for Visibility Enhancement; 3.1 Preliminaries and Summary of Contributions; 3.2 Restorability Formulation; 3.2.1 Terminologies; 3.2.2 Gate-Level Restorabilities; 3.3 Trace Signal Selection; 3.3.1 Circuit Level Visibility Calculation. 3.3.2 Trace Signal Selection Methodology3.3.3 Trace Signal Selection Enhancements; 3.4 Experimental Results; 3.4.1 Experiment Setup; 3.4.2 Experimental Results; 3.5 Conclusion; 4 Multiplexed Tracing for Design Error; 4.1 Preliminaries and Summary of Contributions; 4.2 Design Error Visibility Metric; 4.3 Proposed Methodology; 4.3.1 Supporting DfD Hardware for Multiplexed Signal Tracing; 4.3.2 Signal Grouping Algorithm; 4.4 Experimental Results; 4.4.1 Experiment Setup; 4.4.2 Experimental Results; 4.5 Conclusion; 5 Tracing for Electrical Error; 5.1 Preliminaries and Summary of Contributions. 5.2 Observing Speedpath-Related Electrical Errors5.2.1 Speedpath-Related Electrical Error Model; 5.2.2 Speedpath-Related Electrical Error Detection Quality; 5.3 Trace Signal Selection; 5.3.1 Relation Cube Extraction; 5.3.2 Signal Selection for Non-Zero-Probability Error Detection; 5.3.3 Trace Signal Selection for Error Detection Quality Enhancement; 5.4 Trace Data Qualification; 5.5 Experimental Results; 5.6 Conclusion; 6 Reusing Test Access Mechanisms; 6.1 Preliminaries and Summary of Contributions; 6.1.1 SoC Test Architectures; 6.1.2 SoC Post-Silicon Validation Architectures. 6.1.3 Summary of Contributions6.2 Overview of the Proposed Debug Data Transfer Framework; 6.3 Proposed DfD Structures; 6.3.1 Modified Wrapper Design; 6.3.2 Trace Buffer Interface Design; 6.4 Sharing TAM for Multi-Core Debug Data Transfer; 6.4.1 Core Masking for TestRail Architecture; 6.4.2 Channel Split; 6.5 Experimental Results; 6.6 Conclusion; 7 Interconnection Fabric for Flexible Tracing; 7.1 Preliminaries and Summary of Contributions; 7.2 Proposed Interconnection Fabric Design; 7.2.1 Multiplexer Network for Mutually-Exclusive Signals. 7.2.2 Non-Blocking Concentration Network for Concurrently-Accessible Signals7.3 Experimental Results; 7.4 Conclusion; 8 Interconnection Fabric for Systematic Tracing; 8.1 Preliminaries and Summary of Contributions; 8.2 Proposed Trace Interconnection Fabric; 8.3 Proposed Error Evidence Localization Methodology; 8.4 Experimental Results; 8.4.1 Experimental Setup; 8.4.2 Results and Discussion; 8.5 Conclusion; 9 Conclusion; References; Index.
Series Title: Lecture notes in electrical engineering.

Abstract:

This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits. The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective. A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tra.

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