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Transactional memory

Author: James R Larus; Ravi Rajwar
Publisher: [San Rafael, Calif.] : Morgan & Claypool, ©2007.
Series: Synthesis lectures in computer architecture (Online), #2.
Edition/Format:   eBook : Document : Biography : English : 1st edView all editions and formats
Summary:
The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Material Type: Biography, Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: James R Larus; Ravi Rajwar
ISBN: 1598291246 9781598291247 1598291254 9781598291254
OCLC Number: 77563656
Description: 1 online resource (xiii, 211 pages).
Contents: IntroductionProgramming Transactional MemorySoftware Transactional MemoryHardware-Supported Transactional MemoryConclusions
Series Title: Synthesis lectures in computer architecture (Online), #2.
Responsibility: James R. Larus, Ravi Rajwar.

Abstract:

The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This book offers an alternative way to  Read more...

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Linked Data


Primary Entity

<http://www.worldcat.org/oclc/77563656> # Transactional memory
    a schema:MediaObject, schema:CreativeWork, schema:Book ;
   library:oclcnum "77563656" ;
   library:placeOfPublication <http://id.loc.gov/vocabulary/countries/cau> ;
   library:placeOfPublication <http://experiment.worldcat.org/entity/work/data/3372926313#Place/san_rafael_calif> ; # San Rafael, Calif.
   schema:about <http://id.worldcat.org/fast/1141085> ; # Synchronization
   schema:about <http://dewey.info/class/004.22/> ;
   schema:about <http://id.worldcat.org/fast/1150298> ; # Threads (Computer programs)
   schema:about <http://id.worldcat.org/fast/1154510> ; # Transaction systems (Computer systems)
   schema:about <http://id.worldcat.org/fast/1052939> ; # Parallel programming (Computer science)
   schema:bookEdition "1st ed." ;
   schema:bookFormat schema:EBook ;
   schema:contributor <http://viaf.org/viaf/78547496> ; # Ravi Rajwar
   schema:copyrightYear "2007" ;
   schema:creator <http://viaf.org/viaf/250854646> ; # James R. Larus
   schema:datePublished "2007" ;
   schema:description "The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically -- either it completes successfully."@en ;
   schema:exampleOfWork <http://worldcat.org/entity/work/id/3372926313> ;
   schema:genre "Biography"@en ;
   schema:genre "Electronic books"@en ;
   schema:inLanguage "en" ;
   schema:isPartOf <http://experiment.worldcat.org/entity/work/data/3372926313#Series/synthesis_lectures_on_computer_architecture> ; # Synthesis lectures on computer architecture ;
   schema:isPartOf <http://experiment.worldcat.org/entity/work/data/3372926313#Series/synthesis_lectures_in_computer_architecture_online> ; # Synthesis lectures in computer architecture (Online) ;
   schema:isSimilarTo <http://worldcat.org/entity/work/data/3372926313#CreativeWork/> ;
   schema:name "Transactional memory"@en ;
   schema:productID "77563656" ;
   schema:publication <http://www.worldcat.org/title/-/oclc/77563656#PublicationEvent/san_rafael_calif_morgan_&_claypool_2007> ;
   schema:publisher <http://experiment.worldcat.org/entity/work/data/3372926313#Agent/morgan_&_claypool> ; # Morgan & Claypool
   schema:url <http://uri.idm.oclc.org/login?url=http://dx.doi.org/10.2200/S00070ED1V01Y200611CAC002> ;
   schema:url <http://site.ebrary.com/id/10515663> ;
   schema:url <http://www.morganclaypool.com/doi/abs/10.2200/S00070ED1V01Y200611CAC002> ;
   schema:workExample <http://worldcat.org/isbn/9781598291247> ;
   schema:workExample <http://worldcat.org/isbn/9781598291254> ;
   wdrs:describedby <http://www.worldcat.org/title/-/oclc/77563656> ;
    .


Related Entities

<http://experiment.worldcat.org/entity/work/data/3372926313#Agent/morgan_&_claypool> # Morgan & Claypool
    a bgn:Agent ;
   schema:name "Morgan & Claypool" ;
    .

<http://experiment.worldcat.org/entity/work/data/3372926313#Place/san_rafael_calif> # San Rafael, Calif.
    a schema:Place ;
   schema:name "San Rafael, Calif." ;
    .

<http://experiment.worldcat.org/entity/work/data/3372926313#Series/synthesis_lectures_in_computer_architecture_online> # Synthesis lectures in computer architecture (Online) ;
    a bgn:PublicationSeries ;
   schema:hasPart <http://www.worldcat.org/oclc/77563656> ; # Transactional memory
   schema:name "Synthesis lectures in computer architecture (Online) ;" ;
    .

<http://experiment.worldcat.org/entity/work/data/3372926313#Series/synthesis_lectures_on_computer_architecture> # Synthesis lectures on computer architecture ;
    a bgn:PublicationSeries ;
   schema:hasPart <http://www.worldcat.org/oclc/77563656> ; # Transactional memory
   schema:name "Synthesis lectures on computer architecture ;" ;
    .

<http://id.worldcat.org/fast/1052939> # Parallel programming (Computer science)
    a schema:Intangible ;
   schema:name "Parallel programming (Computer science)"@en ;
    .

<http://id.worldcat.org/fast/1141085> # Synchronization
    a schema:Intangible ;
   schema:name "Synchronization"@en ;
    .

<http://id.worldcat.org/fast/1150298> # Threads (Computer programs)
    a schema:Intangible ;
   schema:name "Threads (Computer programs)"@en ;
    .

<http://id.worldcat.org/fast/1154510> # Transaction systems (Computer systems)
    a schema:Intangible ;
   schema:name "Transaction systems (Computer systems)"@en ;
    .

<http://viaf.org/viaf/250854646> # James R. Larus
    a schema:Person ;
   schema:familyName "Larus" ;
   schema:givenName "James R." ;
   schema:name "James R. Larus" ;
    .

<http://viaf.org/viaf/78547496> # Ravi Rajwar
    a schema:Person ;
   schema:familyName "Rajwar" ;
   schema:givenName "Ravi" ;
   schema:name "Ravi Rajwar" ;
    .

<http://worldcat.org/isbn/9781598291247>
    a schema:ProductModel ;
   schema:isbn "1598291246" ;
   schema:isbn "9781598291247" ;
    .

<http://worldcat.org/isbn/9781598291254>
    a schema:ProductModel ;
   schema:isbn "1598291254" ;
   schema:isbn "9781598291254" ;
    .


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