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Utleon3 : exploring fine-grain multi-threading in FPGAs

Author: Martin Daněk
Publisher: New York : Springer, ©2013.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Database:WorldCat
Summary:
This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical  Read more...
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Details

Genre/Form: Electronic books
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Martin Daněk
ISBN: 9781461424109 1461424100
OCLC Number: 818413973
Description: 1 online resource
Contents: Introduction --
The LEON3 Processor --
Microthreaded Extensions --
The Basic UTLEON3 Architecture.- UTLEON3 Programming by Example --
UTLEON3 Implementation Details --
Execution Effieciency of the Microthread Pipeline.- Hardware Families of Threads --
I/O and Interrupt Handling in the Microthread Mode --
The IU3 Pipeline --
Excerpts from the LEON3 Instruction Set --
Relevant LEON3 Registers and Address Space Identifiers.- Scheduler Example --
Used Resources --
Tutorial.
Responsibility: Martin Daněk [and others].

Abstract:

This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs. Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch;Provides VHDL sources for the described processor;Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines;Includes programming by example in the micro-threaded assembly language.

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