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The VLSI handbook

Author: Wai-Kai Chen
Publisher: Boca Raton, Fla. : CRC Press ; [New York] : IEEE Press, ©2000.
Series: Electrical engineering handbook series.
Edition/Format:   eBook : Document : EnglishView all editions and formats

Over the years, the fundamentals of VLSI technology have evolved to include a wide range of topics and a broad range of practice. This handbook focuses on the key concepts, models, and equations that  Read more...


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Genre/Form: Electronic books
Additional Physical Format: Print version:
VLSI handbook.
Boca Raton, Fla. : CRC Press ; [New York] : IEEE Press, ©2000
(DLC) 99047682
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Wai-Kai Chen
ISBN: 9781420049671 1420049674
OCLC Number: 47101497
Description: 1 online resource (1 volume (various pagings)) : illustrations.
Contents: VLSIVLSI Technology: A System PerspectiveCMOS/BiCMOS TechnologyBipolar TechnologySilicon on Insulator TechnologySiGe TechnologySiC TechnologyPassive ComponentsPower IC TechnologiesNoise in VLSI TechnologiesMicromachiningMicroelectronics PackagingMultichip Module TechnologiesChannel Hot Electron Degradation-Delay in MOS Transistors Due to Deuterium AnnealDevices and Their ModelsBipolar Junction Transistor (BJT) CircuitsRF Passive IC ComponentsCircuit SimulationsAnalog Circuit SimulationInterconnect Modeling and SimulationPower Simulation and Estimation in VLSI CircuitsAmplifiersCMOS Amplifier DesignBipolar Amplifier DesignHigh-Frequency AmplifiersOperational Transconductance AmplifiersLogic CircuitsExpressions of Logic FunctionsBasic Theory of Logic FunctionsSimplification of Logic ExpressionsBinary Decision DiagramsLogic Synthesis with AND and OR Gates in Two LevelsSequential Networks with AND and OR GatesLogic Synthesis with AND and OR Gates in Multi-LevelsLogic Properties of Transistor CircuitsLogic Synthesis with NAND (or NOR) Gates in Multi-LevelsLogic Synthesis with a Minimum Number of Negative GatesLogic Synthesizer with Optimizations in Two PhasesLogic Synthesizer by the Transduction MethodEmitter-Coupled LogicCMOSPass TransistorsAddersMultipliersDividersFull-Custom and Semi-Custom DesignProgrammable Logic DevicesGate ArraysField-Programmable Gate ArraysCell-Library Design ApproachComparison of Different Design ApproachesMemory, Registers, and System TimingSystem TimingROM/PROM/EPROMSRAMEmbedded MemoryFlash MemoriesDynamic Random Access MemoryLow-Power Memory CircuitsAnalog CircuitsNyquist-Rate ADC and DACOversampled Analog-to-Digital and Digital-to-Analog ConvertersRF Communication CircuitsPLL CircuitsContinuous-Time FiltersSwitched-Capacitor FiltersMicroprocessor and ASICTiming and Signal Integrity AnalysisMicroprocessor Design VerificationMicroprocessor Layout MethodArchitectureASIC DesignLogic Synthesis for Field Programmable Gate Array (FPGA) TechnologyTest and TestabilityTestability Concepts and DFTATPG and BISTCAD Tools for BIST/DFT and Delay FaultsCompound Semiconductor Digital Integrated Circuit TechnologyMaterialsCompound Semiconductor Devices for Digital CircuitsLogic Design Principles and ExamplesLogic Design ExamplesDesign AutomationInternet Based Micro-Electronic Design Automation (IMEDA) FrameworkSystem -Level DesignSynthesis at the Register Transfer Level and the Behavioral LevelPerformance Modeling and Analysis in VHDLEmbedded Computing Systems and Hardware/Software Co-DesignDesign Automation Technology RoadmapAlgorithms and ArchitectAlgorithms and Architectures for Multimedia and Beamforming Array Processings in Communication SystemsDesign LanguagesDesign LanguagesHardware Description in Verilog: An Introductory Tutorial
Series Title: Electrical engineering handbook series.
Responsibility: editor-in-chief, Wai-Kai Chen.


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