skip to content

Lubaszewski, Marcelo

Overview
Works: 24 works in 63 publications in 3 languages and 1,036 library holdings
Genres: Conference papers and proceedings 
Roles: Author, Editor, Creator, Thesis advisor
Publication Timeline
Key
Publications about Marcelo Lubaszewski
Publications by Marcelo Lubaszewski
Most widely held works by Marcelo Lubaszewski
Design of system on a chip : devices & components by Ricardo A. L Reis( Book )
19 editions published between 2006 and 2010 in English and Undetermined and held by 145 libraries worldwide
Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered. Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications
XII Symposium on Integrated Circuits and Systems Design : proceedings : Natal-RN, Brazil, September 29-October 2, 1999 by Symposium on Integrated Circuits and Systems Design( Book )
8 editions published between 1999 and 2002 in English and held by 46 libraries worldwide
XI Brazilian Symposium on Integrated Circuit Design : proceedings : September 30-October 3, 1998, Armação de Búzios, Rio de Janeiro, Brazil by Simpósio de Concepção de Circuitos Integrados( Book )
8 editions published between 1998 and 2002 in English and held by 41 libraries worldwide
Testing chips with mesh-based network-on-chip by Alexandre Amory( Book )
1 edition published in 2009 in English and held by 4 libraries worldwide
B²UBIST : a strategy for boundary scan board unified BIST by Marcelo Lubaszewski( Book )
3 editions published in 1991 in English and held by 4 libraries worldwide
Abstract: "In this paper, boundary scan and UBIST techniques are combined in order to propose a solution to obtain an efficient test strategy for circuits and boards. This results in a hierarchical strategy covering all types of tests necessary to boards, e.g. off-line test and concurrent error detection for circuits and connections. Fault diagnosis is briefly addressed herein."
Design of systems on a chip design and test ( file )
1 edition published in 2007 in English and held by 4 libraries worldwide
SBCCI'99 : Symposium on integrated circuits and systems design : proceedings : September 29-October 2, 1999, Natal, RN, Brazil by Simpósio de Concepção de Circuitos Integrados( Book )
1 edition published in 1999 in English and held by 3 libraries worldwide
Proceedings of the 21st annual Symposium on Integrated Circuits and System Design September 1-4, 2008, Gramado, Brazil by Marcelo Lubaszewski( Book )
3 editions published in 2008 in English and held by 3 libraries worldwide
Le test unifié de cartes appliqué à la conception de systèmes fiables by Marcelo Lubaszewski( Book )
2 editions published in 1994 in French and held by 2 libraries worldwide
Si on veut assurer de facon efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amene a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre etendue du niveau circuit aux niveaux carte et module. D'autre part, bien que l'integration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute surete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confrontee a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les etapes intermediaires de l'evolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite l'etape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa sureté inherente
SBCCI2008 : proceedings : 21st Symposium on Integrated Circuits and Systems Design : Gramado, Brazil, September 1 to 4, 2008 : Chip in the Pampa by Symposium on Integrated Circuits and Systems Design( Book )
2 editions published in 2008 in English and held by 2 libraries worldwide
Proceedings : September 30 - October 3, 1998, Armação de Búzios, Rio de Janeiro, Brazil by Symposium on Integrated Circuits and Systems Design( Book )
2 editions published in 1998 in English and held by 2 libraries worldwide
SBCCI 99 proceedings, September 29-October 3 1999, Natal, RN, Brazil by Symposium on Integrated Circuits and Systems Design( Book )
1 edition published in 1999 in English and held by 1 library worldwide
ATPG para teste de circuitos analógicos e mistos by Érika Fernandes Cota( Book )
1 edition published in 1997 in Portuguese and held by 1 library worldwide
Special issue on the First Latin-American Test Workshop : [held in Rio de Janeiro, Brazil, during March 13-15, 2000] by Latin American Test Workshop( Book )
1 edition published in 2001 in English and held by 1 library worldwide
Proceedings : X Brazilian Symposium on Integrated Circuit Design - SBCCI, August 25-27, 1997, Gramado, RS, Brazil by Simpósio de Concepção de Circuitos Integrados( Book )
1 edition published in 1997 in English and held by 1 library worldwide
Special issue on the First IEEE Latin-American Test Workshop by Latin-American Test Workshop( Book )
1 edition published in 2001 in English and held by 1 library worldwide
SBCCI 2008: 21st annual Symposium on Integrated Circuits and System Design : September 1-4, 2008, Gramado, Brazil, Chip in the Pampa by Symposium on Integrated Circuits and Systems Design( Book )
1 edition published in 2008 in English and held by 1 library worldwide
SBCCI'97 Proceedings : X Brazilian Symposium on Integrated Circuit Design - SBCCI = X Simposio Brasileiro de Concepçao de Circuitos Integrados - SBCCI : August 25-27, 1997, Gramado, RS, Brazil by Brazilian Symposium on Integrated Circuit Design( Book )
1 edition published in 1997 in English and held by 1 library worldwide
 
moreShow More Titles
fewerShow Fewer Titles
Languages
English (55)
French (2)
Portuguese (1)
Covers
Close Window

Please sign in to WorldCat 

Don't have an account? You can easily create a free account.