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Lubaszewski, Marcelo

Overview
Works: 24 works in 51 publications in 3 languages and 803 library holdings
Genres: Conference proceedings 
Roles: Author, Editor, Creator, Thesis advisor
Classifications: TK7895.E42, 621.3815
Publication Timeline
Key
Publications about Marcelo Lubaszewski
Publications by Marcelo Lubaszewski
Most widely held works by Marcelo Lubaszewski
Design of systems on a chip design and test by Ricardo Reis( file )
18 editions published between 2006 and 2010 in English and held by 465 libraries worldwide
XI Brazilian Symposium on Integrated Circuit Design proceedings, September 30-October 3, 1998, Armação de Búzios, Rio de Janeiro, Brazil by Simpósio de Concepção de Circuitos Integrados( Computer File )
5 editions published between 1998 and 2002 in English and held by 154 libraries worldwide
XII Symposium on Integrated Circuits and Systems Design proceedings : Natal-RN, Brazil, September 29-October 2, 1999 by Simpósio de Concepção de Circuitos Integrados( file )
3 editions published in 1999 in English and held by 136 libraries worldwide
XII Symposium on Integrated Circuits and Systems Design : Natal--RN, Brazil, September 29-October 2, 1999 : proceedings by Symposium on Integrated Circuits and Systems Design( Book )
2 editions published between 1999 and 2002 in English and held by 10 libraries worldwide
Proceedings of the 21st annual symposium on Integrated circuits and system design by Marcelo Lubaszewski( file )
2 editions published in 2008 in English and held by 6 libraries worldwide
Reliability, availability and serviceability of networks-on-chip by Érika Cota( Book )
1 edition published in 2011 in English and held by 4 libraries worldwide
Annotation
Testing chips with mesh-based network-on-chip by Alexandre Amory( Book )
1 edition published in 2009 in English and held by 4 libraries worldwide
Proceedings of the 21st annual Symposium on Integrated Circuits and System Design : September 1-4, 2008, Gramado, Brazil by Symposium on Integrated Circuits and Systems Design( Book )
1 edition published in 2008 in English and held by 3 libraries worldwide
SBCCI'99 : Symposium on integrated circuits and systems design : proceedings : September 29-October 2, 1999, Natal, RN, Brazil by Simpósio de Concepção de Circuitos Integrados( Book )
1 edition published in 1999 in English and held by 3 libraries worldwide
Proceedings September 30-October 3 1998, Armação de Buzios, Rio de Janeiro, Brasil by Symposium on Integrated Circuits and Systems Design( Book )
2 editions published in 1998 in English and held by 2 libraries worldwide
Le test unifie de cartes applique a la conception de systemes faibles by Marcelo Lubaszewski( Book )
2 editions published in 1994 in French and held by 2 libraries worldwide
SI ON VEUT ASSURER DE FACON EFFICACE LES TESTS DE CONCEPTION, DE FABRICATION, DE MAINTENANCE ET LE TEST ACCOMPLI AU COURS DE L'APPLICATION POUR LES SYSTEMES ELECTRONIQUES, ON EST AMENE A INTEGRER LE TEST HORS-LIGNE ET LE TEST EN-LIGNE DANS DES CIRCUITS. ENSUITE, POUR QUE LES SYSTEMES COMPLEXES TIRENT PROFIT DES DEUX TYPES DE TESTS, UNE TELLE UNIFICATION DOIT ETRE ETENDUE DU NIVEAU CIRCUIT AUX NIVEAUX CARTE ET MODULE. D'AUTRE PART, BIEN QUE L'INTEGRATION DES TECHNIQUES DE TEST HORS-LIGNE ET EN-LIGNE FAIT QU'IL EST POSSIBLE DE CONCEVOIR DES SYSTEMES POUR TOUTE APPLICATION SECURITAIRE, LE MATERIEL AJOUTE POUR ASSURER UNE HAUTE SURETE DE FONCTIONNEMENT FAIT QUE LA FIABILITE DE CES SYSTEMES EST REDUITE, CAR LA PROBABILITE D'OCCURENCE DE FAUTES AUGMENTE. CONFRONTEE A CES DEUX ASPECTS ANTAGONIQUES, CETTE THESE SE FIXE L'OBJECTIF DE TROUVER UN COMPROMIS ENTRE LA SECURITE ET LA FIABILITE DE SYSTEMES ELECTRONIQUES COMPLEXES. AINSI, DANS UN PREMIER TEMPS, ON PROPOSE UNE SOLUTION AUX PROBLEMES DE TEST HORS-LIGNE ET DE DIAGNOSTIC QUI SE POSENT DANS LES ETAPES INTERMEDIAIRES DE L'EVOLUTION VERS LES CARTES 100% COMPATIBLES AVEC LE STANDARD IEEE 1149.1 POUR LE TEST BOUNDARY SCAN. UNE APPROCHE POUR LE BIST (BUILT-IN SELF-TEST) DES CIRCUITS ET CONNEXIONS BOUNDARY SCAN ILLUSTRE ENSUITE L'ETAPE ULTIME DU TEST HORS-LIGNE DE CARTES. PUIS, LE SCHEMA UBIST (UNIFIED BIST) INTEGRANT LES TECHNIQUES BIST ET SELF-CHECKING POUR LE TEST EN-LIGNE DE CIRCUITS, EST COMBINE AU STANDARD IEEE 1149.1, AFIN D'OBTENIR UNE STRATEGIE DE CONCEPTION EN VUE DU TEST UNIFIE DE CONNEXIONS ET CIRCUITS MONTES SUR DES CARTES ET MODULES. ENFIN, ON PROPOSE UN SCHEMA TOLERANT LES FAUTES ET BASE SUR LA DUPLICATION DE CES MODULES SECURITAIRES QUI ASSURE LA COMPETITIVITE DU SYSTEME RESULTANT DU POINT DE VUE DE LA FIABILITE, TOUT EN GARDANT SA SURETE INHERENTE
SBCCI 99 proceedings, September 29-October 3 1999, Natal, RN, Brazil by Symposium on Integrated Circuits and Systems Design( Book )
1 edition published in 1999 in English and held by 1 library worldwide
SBCCI'97 by Brazilian Symposium on Integrated Circuit Design( Book )
1 edition published in 1997 in English and held by 1 library worldwide
SBCCI 2008: 21st annual Symposium on Integrated Circuits and System Design : September 1-4, 2008, Gramado, Brazil, Chip in the Pampa by Symposium on Integrated Circuits and Systems Design( Book )
1 edition published in 2008 in English and held by 1 library worldwide
Special issue on the First IEEE Latin-American Test Workshop by IEEE Latin-American Test Workshop( Book )
1 edition published in 2001 in English and held by 1 library worldwide
Special issue on the First Latin-American Test Workshop : [held in Rio de Janeiro, Brazil, during March 13 - 15, 2000] by Latin American Test Workshop( Book )
1 edition published in 2001 in English and held by 1 library worldwide
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1 edition published in 2007 in English and held by 1 library worldwide
Proceedings : X Brazilian Symposium on Integrated Circuit Design - SBCCI, August 25-27, 1997, Gramado, RS, Brazil by Simpósio de Concepção de Circuitos Integrados( Book )
1 edition published in 1997 in English and held by 1 library worldwide
ATPG para teste de circuitos analógicos e mistos by Érika Fernandes Cota( Book )
1 edition published in 1997 in Portuguese and held by 1 library worldwide
 
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Languages
English (43)
French (2)
Portuguese (1)
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