Leiserson, Charles Eric
Overview
Works:  91 works in 387 publications in 8 languages and 3,060 library holdings 

Genres:  Conference papers and proceedings 
Roles:  Author, Editor, Other 
Classifications:  QA76.6, 005.1 
Publication Timeline
.
Most widely held works by
Charles Eric Leiserson
Introduction to algorithms by
Thomas H Cormen(
Book
)
132 editions published between 1989 and 2017 in 6 languages and held by 2,006 WorldCat member libraries worldwide
Some books on algorithms are rigorous but incomplete; others cover masses of material but lack rigor. Introduction to Algorithms uniquely combines rigor and comprehensiveness. The book covers a broad range of algorithms in depth, yet makes their design and analysis accessible to all levels of readers. Each chapter is relatively selfcontained and can be used as a unit of study. The algorithms are described in English and in a pseudocode designed to be readable by anyone who has done a little programming. The explanations have been kept elementary without sacrificing depth of coverage or mathematical rigor.  The first edition became a widely used text in universities worldwide as well as the standard reference for professionals. The second edition featured new chapters on the role of algorithms, probabilistic analysis and randomized algorithms, and linear programming. The third edition has been revised and updated throughout. It includes two completely new chapters, on van Emde Boas trees and multithreaded algorithms, and substantial additions to the chapter on recurrences (now called "DivideandConquer"). It features improved treatment of dynamic programming and greedy algorithms and a new notion of edgebased flow in the material on flow networks. Many new exercises and problems have been added for this edition
132 editions published between 1989 and 2017 in 6 languages and held by 2,006 WorldCat member libraries worldwide
Some books on algorithms are rigorous but incomplete; others cover masses of material but lack rigor. Introduction to Algorithms uniquely combines rigor and comprehensiveness. The book covers a broad range of algorithms in depth, yet makes their design and analysis accessible to all levels of readers. Each chapter is relatively selfcontained and can be used as a unit of study. The algorithms are described in English and in a pseudocode designed to be readable by anyone who has done a little programming. The explanations have been kept elementary without sacrificing depth of coverage or mathematical rigor.  The first edition became a widely used text in universities worldwide as well as the standard reference for professionals. The second edition featured new chapters on the role of algorithms, probabilistic analysis and randomized algorithms, and linear programming. The third edition has been revised and updated throughout. It includes two completely new chapters, on van Emde Boas trees and multithreaded algorithms, and substantial additions to the chapter on recurrences (now called "DivideandConquer"). It features improved treatment of dynamic programming and greedy algorithms and a new notion of edgebased flow in the material on flow networks. Many new exercises and problems have been added for this edition
Areaefficient VLSI computation by
Charles Eric Leiserson(
Book
)
23 editions published between 1981 and 1987 in English and Undetermined and held by 310 WorldCat member libraries worldwide
The two parts of this thesis address two measures of efficiency. Part 1 analyzes systolic systems which marry the ideas of pipelining and multiprocessing in a single framework of design. Part II looks at the layout of their communication paths. Although the two parts fit together, it should be understood that the ideas in each stand alone. The results of Part I can be applied to systems which are not systolic, and even systems which are not assembled on integrated circuits. The layout results of Part II can be applied to more general communication structures than graphs of systolic systems, and the ideas for representing layouts can be used in other routing algorithms
23 editions published between 1981 and 1987 in English and Undetermined and held by 310 WorldCat member libraries worldwide
The two parts of this thesis address two measures of efficiency. Part 1 analyzes systolic systems which marry the ideas of pipelining and multiprocessing in a single framework of design. Part II looks at the layout of their communication paths. Although the two parts fit together, it should be understood that the ideas in each stand alone. The results of Part I can be applied to systems which are not systolic, and even systems which are not assembled on integrated circuits. The layout results of Part II can be applied to more general communication structures than graphs of systolic systems, and the ideas for representing layouts can be used in other routing algorithms
Advanced research in VLSI : proceedings of the fourth MIT conference, April 79, 1986 by
1986, Cambridge, Mass.> Conference on Advanced Research in VLSI. <4(
Book
)
12 editions published in 1986 in 3 languages and held by 223 WorldCat member libraries worldwide
12 editions published in 1986 in 3 languages and held by 223 WorldCat member libraries worldwide
Introduction à l'algorithmique by
Thomas H Cormen(
Book
)
7 editions published between 1994 and 2000 in French and held by 152 WorldCat member libraries worldwide
7 editions published between 1994 and 2000 in French and held by 152 WorldCat member libraries worldwide
Retiming synchronous circuitry by
Charles Eric Leiserson(
Book
)
12 editions published between 1986 and 1988 in English and Undetermined and held by 28 WorldCat member libraries worldwide
This paper shows how the technique of retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph, and we give an O(/V/ /E/lg/V/) algorithm for determining an equivalent circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomialtime solvable. This result yields a polynomialtime optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a characterization of optimal retiming based on an efficiently solvable mixedinteger linear programming problem. (Author)
12 editions published between 1986 and 1988 in English and Undetermined and held by 28 WorldCat member libraries worldwide
This paper shows how the technique of retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph, and we give an O(/V/ /E/lg/V/) algorithm for determining an equivalent circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomialtime solvable. This result yields a polynomialtime optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a characterization of optimal retiming based on an efficiently solvable mixedinteger linear programming problem. (Author)
Introduzione agli algoritmi by
Thomas H Cormen(
Book
)
7 editions published between 1994 and 2003 in Italian and English and held by 23 WorldCat member libraries worldwide
7 editions published between 1994 and 2003 in Italian and English and held by 23 WorldCat member libraries worldwide
Optimizing synchronous systems by
Charles Eric Leiserson(
Book
)
6 editions published between 1981 and 1982 in English and Undetermined and held by 17 WorldCat member libraries worldwide
6 editions published between 1981 and 1982 in English and Undetermined and held by 17 WorldCat member libraries worldwide
Wprowadzenie do algorytmów by
Thomas H Cormen(
Book
)
10 editions published between 1997 and 2018 in Polish and held by 14 WorldCat member libraries worldwide
10 editions published between 1997 and 2018 in Polish and held by 14 WorldCat member libraries worldwide
Optimal placement for river routing by
Charles Eric Leiserson(
Book
)
8 editions published between 1981 and 1987 in English and held by 14 WorldCat member libraries worldwide
Programs for integrated circuit layout typically have two phases: placement and routing. The router should produce as efficient a layout as possible, but of course the quality of the routing depends heavily on the quality of the placement. On the other hand, the placement procedure ideally should know the quality of a routing before it routes the wires. In this talk we present an optimal solution for a practical, common version of this placement and routing problem. (Author)
8 editions published between 1981 and 1987 in English and held by 14 WorldCat member libraries worldwide
Programs for integrated circuit layout typically have two phases: placement and routing. The router should produce as efficient a layout as possible, but of course the quality of the routing depends heavily on the quality of the placement. On the other hand, the placement procedure ideally should know the quality of a routing before it routes the wires. In this talk we present an optimal solution for a practical, common version of this placement and routing problem. (Author)
A mixedinteger linear programming problem which is efficiently solvable by
Charles Eric Leiserson(
Book
)
7 editions published between 1984 and 1987 in English and held by 11 WorldCat member libraries worldwide
Much research has centered on the problem of finding shortest paths in graphs. It is well known that there is a direct correspondence between the single source shortestpaths problem and the following simple linear programming problems: Let S be a set of linear inequalities of the form x sub j  x sub i <or = (a sub ij, where the x sub i are unknowns and the a sub ij are given real constants. Determine a set of values for the x sub i such that the inequalities in S are satisfied, or determine that no such values exist. This paper considers the mixedinteger linear programming variant of this problem in which some (but not necessarily all) of the x sub i are required to be integers. The problem arises in the context of synchronous circuit optimization but it has applications to PERT scheduling and VLSI layout compaction as well. Keywords: Algorithms, Combinatorial optimization
7 editions published between 1984 and 1987 in English and held by 11 WorldCat member libraries worldwide
Much research has centered on the problem of finding shortest paths in graphs. It is well known that there is a direct correspondence between the single source shortestpaths problem and the following simple linear programming problems: Let S be a set of linear inequalities of the form x sub j  x sub i <or = (a sub ij, where the x sub i are unknowns and the a sub ij are given real constants. Determine a set of values for the x sub i such that the inequalities in S are satisfied, or determine that no such values exist. This paper considers the mixedinteger linear programming variant of this problem in which some (but not necessarily all) of the x sub i are required to be integers. The problem arises in the context of synchronous circuit optimization but it has applications to PERT scheduling and VLSI layout compaction as well. Keywords: Algorithms, Combinatorial optimization
SPAA, 97: 9th Annual ACM Symposium on Parallel Algoriths and Architectures by
Charles Eric Leiserson(
)
2 editions published in 1997 in English and held by 11 WorldCat member libraries worldwide
2 editions published in 1997 in English and held by 11 WorldCat member libraries worldwide
Waferscale integration of systolic arrays by
Frank Thomson Leighton(
Book
)
6 editions published between 1983 and 1985 in English and held by 11 WorldCat member libraries worldwide
VLSI technologies are fast developing waferscale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind waferscale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating waferscale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NPcomplete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, faulttolerant systems and planar geometry
6 editions published between 1983 and 1985 in English and held by 11 WorldCat member libraries worldwide
VLSI technologies are fast developing waferscale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind waferscale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating waferscale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NPcomplete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, faulttolerant systems and planar geometry
The organization of permutation architectures with bussed interconnections by
Joe Kilian(
Book
)
6 editions published between 1987 and 1989 in English and held by 10 WorldCat member libraries worldwide
This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to pointtopoint interconnections, the number of pins per chip can often be reduced. For example, for infinitely many n, permutation architectures are exhibited with Sq. rt. n pins per chip that can realize any of the n cyclic shifts on n chips in one clock tick. When the set of permutations forms a group with p elements, any permutation in the group can be realized in one clock tick by an architecture with 0 (Sq. rt. (p1g p) pins per chip. When the permutation group is abelian, 0 (Sq. rt. p) pins suffice. These results are all derived from a mathematical characterization of uniform permutation architectures based on the combinatorial notion of a difference cover. Consider uniform permutation architectures that realize permutations in several clock ticks, instead of one, further savings is shown in the number of pins per chip can be obtained. Keywords: Barrel shifter, Bussed interconnections, Cyclic shifter, Difference cover, Difference set, Group theory, Permutation, Permutation architecture, Projective plane, Specialpurpose architecture, Uniform architecture, Reprints. (JHD)
6 editions published between 1987 and 1989 in English and held by 10 WorldCat member libraries worldwide
This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to pointtopoint interconnections, the number of pins per chip can often be reduced. For example, for infinitely many n, permutation architectures are exhibited with Sq. rt. n pins per chip that can realize any of the n cyclic shifts on n chips in one clock tick. When the set of permutations forms a group with p elements, any permutation in the group can be realized in one clock tick by an architecture with 0 (Sq. rt. (p1g p) pins per chip. When the permutation group is abelian, 0 (Sq. rt. p) pins suffice. These results are all derived from a mathematical characterization of uniform permutation architectures based on the combinatorial notion of a difference cover. Consider uniform permutation architectures that realize permutations in several clock ticks, instead of one, further savings is shown in the number of pins per chip can be obtained. Keywords: Barrel shifter, Bussed interconnections, Cyclic shifter, Difference cover, Difference set, Group theory, Permutation, Permutation architecture, Projective plane, Specialpurpose architecture, Uniform architecture, Reprints. (JHD)
SPAA, 95: 7th Symposium on Parallel Algorithms and Architectures by
Charles Eric Leiserson(
)
2 editions published in 1995 in English and held by 9 WorldCat member libraries worldwide
2 editions published in 1995 in English and held by 9 WorldCat member libraries worldwide
VLSI theory and parallel supercomputing by
Charles Eric Leiserson(
Book
)
3 editions published in 1989 in English and held by 8 WorldCat member libraries worldwide
3 editions published in 1989 in English and held by 8 WorldCat member libraries worldwide
Systolic priority queues by
Charles Eric Leiserson(
Book
)
3 editions published in 1979 in English and held by 8 WorldCat member libraries worldwide
Advances in microelectronics have made the realization of smart data structures a practical reality. VLSI gives us the capability of building logicinmemory hardware that will drastically change how things are computed. Models of computation based solely on the Von Neumann architecture will be insufficient to evaluate algorithms. Multiprocessor devices like the systolic multiqueue will introduce new cost functions to the sequential algorithm designer. But much work must be done to define and examine the models of parallel computation that lie between the mathematical world of computable functions and the physical world of space and time
3 editions published in 1979 in English and held by 8 WorldCat member libraries worldwide
Advances in microelectronics have made the realization of smart data structures a practical reality. VLSI gives us the capability of building logicinmemory hardware that will drastically change how things are computed. Models of computation based solely on the Von Neumann architecture will be insufficient to evaluate algorithms. Multiprocessor devices like the systolic multiqueue will introduce new cost functions to the sequential algorithm designer. But much work must be done to define and examine the models of parallel computation that lie between the mathematical world of computable functions and the physical world of space and time
Areaefficient graph layouts (for VLSI) by
Charles Eric Leiserson(
Book
)
4 editions published between 1980 and 1981 in English and held by 8 WorldCat member libraries worldwide
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph. We give an algorithm that produces VLSI layouts for classes of graphs that have good separator theorems. We show in particular that any planar graph of n vertices has an O(n lgsquare(n)) area layout and that any tree of n vertices can be laid out in linear area. The algorithm maintains a sparse representation for layouts that is based on the wellknown UNIONFIND data structure, and as a result, the running time devoted to management of this representation is nearly linear. (Author)
4 editions published between 1980 and 1981 in English and held by 8 WorldCat member libraries worldwide
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph. We give an algorithm that produces VLSI layouts for classes of graphs that have good separator theorems. We show in particular that any planar graph of n vertices has an O(n lgsquare(n)) area layout and that any tree of n vertices can be laid out in linear area. The algorithm maintains a sparse representation for layouts that is based on the wellknown UNIONFIND data structure, and as a result, the running time devoted to management of this representation is nearly linear. (Author)
Randomized routing on fattrees by
R. I Greenberg(
Book
)
5 editions published between 1985 and 1986 in English and held by 8 WorldCat member libraries worldwide
Fattrees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fattree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda = omega (lg n lg lg n) on a fattree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is o (lambda) with probability 10(1/n). The best previous bound was 0(lambda lg n) for the offline problem where switch settings can be determined in advance. In a VLSIlike model where hardware cost is equated with physical volume, we use the routing algorithm to demonstrate that fattrees are universal routing networks in the sense that any routing network can be efficiently simulated by a fattree of comparable hardware cost. (Author)
5 editions published between 1985 and 1986 in English and held by 8 WorldCat member libraries worldwide
Fattrees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fattree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda = omega (lg n lg lg n) on a fattree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is o (lambda) with probability 10(1/n). The best previous bound was 0(lambda lg n) for the offline problem where switch settings can be determined in advance. In a VLSIlike model where hardware cost is equated with physical volume, we use the routing algorithm to demonstrate that fattrees are universal routing networks in the sense that any routing network can be efficiently simulated by a fattree of comparable hardware cost. (Author)
A timing analysis of levelclocked circuitry by
Alexander T Ishii(
Book
)
5 editions published between 1990 and 1992 in English and held by 7 WorldCat member libraries worldwide
This paper presents an algorithm for verifying proper timing in VLSI circuits where latches are controlled by the levels (high or low) of the controlling clocks rather than the transitions (edges) of the clocks. Such levelclocked circuits are frequently used in MOS VLSI design. A levelclocked circuit is modeled as a graph G = (V, E), where V consists of componentslatches and functional elementsand E represents intercomponent connections. The algorithm verifies the proper timing of a circuit in worstcase O(V/E) time and O(V + E) space. Our analysis decouples the problem of generating timing constraints from the problem of efficiently checking them. We show how various base step functions can be used to provide sufficient conditions for a circuit to operate properly, and we provide a new base step function which is less pessimistic than those used in previous timing verifiers, yet correctly handles timing constraints that are cyclic or extend across the boundaries of multiple clock phases or cycles. The base step function is used to derive a computational expansion of the circuit from which a collection of simple linear constraints are derived. These constraints can be efficiently checked using standard graph algorithms. VLSI systems, Levelclocking, Timing constraints, Timing analysis, Timing verification, Computational expansions, Deltaconstraints, Formal modeling, Graph algorithm applications, Algorithmic techniques
5 editions published between 1990 and 1992 in English and held by 7 WorldCat member libraries worldwide
This paper presents an algorithm for verifying proper timing in VLSI circuits where latches are controlled by the levels (high or low) of the controlling clocks rather than the transitions (edges) of the clocks. Such levelclocked circuits are frequently used in MOS VLSI design. A levelclocked circuit is modeled as a graph G = (V, E), where V consists of componentslatches and functional elementsand E represents intercomponent connections. The algorithm verifies the proper timing of a circuit in worstcase O(V/E) time and O(V + E) space. Our analysis decouples the problem of generating timing constraints from the problem of efficiently checking them. We show how various base step functions can be used to provide sufficient conditions for a circuit to operate properly, and we provide a new base step function which is less pessimistic than those used in previous timing verifiers, yet correctly handles timing constraints that are cyclic or extend across the boundaries of multiple clock phases or cycles. The base step function is used to derive a computational expansion of the circuit from which a collection of simple linear constraints are derived. These constraints can be efficiently checked using standard graph algorithms. VLSI systems, Levelclocking, Timing constraints, Timing analysis, Timing verification, Computational expansions, Deltaconstraints, Formal modeling, Graph algorithm applications, Algorithmic techniques
A spaceefficient algorithm for finding the connected components of rectangles in the plane by
Charles Eric Leiserson(
Book
)
2 editions published in 1987 in English and held by 7 WorldCat member libraries worldwide
2 editions published in 1987 in English and held by 7 WorldCat member libraries worldwide
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Algorithms Combinatorial optimization Computer algorithms Computer architecture Computer programming Computer programmingAbility testing Data structures (Computer science) Electronic circuits Electronic digital computersCircuits Graph theory Graph theoryData processing Integrated circuits Integrated circuitsDesign and construction Integrated circuitsLarge scale integration Integrated circuitsVery large scale integration Linear programmingData processing MicrocomputersBuses Microelectronics Multiprocessors Parallel processing (Electronic computers) Permutations Queuing theory Rectangles Supercomputers Synchronization Trees (Graph theory)Data processing
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Alternative Names
Charles E. Leiserson Amerikaans informaticus
Charles E. Leiserson amerikansk ingeniør og informatikar
Charles E. Leiserson amerikansk ingeniør og informatiker
Charles E. Leiserson amerikansk ingenjör och datavetare
Charles E. Leiserson informaticien américain
Charles E. Leiserson USamerikanischer Forscher
Charles Eric Leiserson
Leiserson, C.
Leiserson, C. E.
Leiserson, Charles
Leiserson, Charles E.
Лейзерсон, Ч.
Лейзерсон, Чарльз Эрик
Чарльз Эрик Лейзерсон
ליזרסון, צ'רלס א.
چارلز ای لیزرسان دانشمند علوم کامپیوتر و مهندس آمریکایی
ライザーソン, C.
ライザーソン, C. E.
查尔斯·雷瑟尔森
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