Front cover image for The Student's Guide to VHDL

The Student's Guide to VHDL

The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses. Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised. In The Student's Guide to VHDL
eBook, English, 2014
Elsevier Science, Burlington, 2014
1 online resource (528 pages).
9780080948553, 0080948553
Preface; 1 Fundamental Concepts; 1.1 Modeling Digital Systems; 1.2 Domains and Levels of Modeling; 1.3 Modeling Languages; 1.4 VHDL Modeling Concepts; 1.5 Learning a New Language: Lexical Elements and Syntax; Exercises; 2 Scalar Data Types and Operations; 2.1 Constants and Variables; 2.2 Scalar Types; 2.3 Type Classification; 2.4 Attributes of Scalar Types; 2.5 Expressions and Predefined Operations; Exercises; 3 Sequential Statements; 3.1 If Statements; 3.2 Case Statements; 3.3 Null Statements; 3.4 Loop Statements; 3.5 Assertion and Report Statements; Exercises. 4 Composite Data Types and Operations4.1 Arrays; 4.2 Unconstrained Array Types; 4.3 Array Operations and Referencing; 4.4 Records; Exercises; 5 Basic Modeling Constructs; 5.1 Entity Declarations and Architecture Bodies; 5.2 Behavioral Descriptions; 5.3 Structural Descriptions; 5.4 Design Processing; Exercises; 6 Subprograms; 6.1 Procedures; 6.2 Procedure Parameters; 6.3 Concurrent Procedure Call Statements; 6.4 Functions; 6.5 Overloading; 6.6 Visibility of Declarations; Exercises; 7 Packages and Use Clauses; 7.1 Package Declarations; 7.2 Package Bodies; 7.3 Use Clauses; Exercises. 8 Resolved Signals8.1 Basic Resolved Signals; 8.2 Resolved Signals, Ports, and Parameters; Exercises; 9 Predefined and Standard Packages; 9.1 The Predefined Packages standard and env; 9.2 IEEE Standard Packages; Exercises; 10 Aliases; 10.1 Aliases for Data Objects; 10.2 Aliases for Non-Data Items; Exercises; 11 Generic Constants; 11.1 Generic Constants; Exercises; 12 Components and Configurations; 12.1 Components; 12.2 Configuring Component Instances; Exercises; 13 Generate Statements; 13.1 Generating Iterative Structures; 13.2 Conditionally Generating Structures; Exercises. 14 Design for Synthesis14.1 Synthesizable Subsets; 14.2 Use of Data Types; 14.3 Interpretation of Standard Logic Values; 14.4 Modeling Combinational Logic; 14.5 Modeling Sequential Logic; 14.6 Modeling Memories; 14.7 Synthesis Attributes; 14.8 Metacomments; Exercises; 15 Case Study: System Design Using the Gumnut Core; 15.1 Overview of the Gumnut; 15.2 A Digital Alarm Clock; Exercises; A Standard Packages; A.1 The Predefined Package standard; A.2 The Predefined Package env; A.3 The Predefined Package textio; A.4 Standard VHDL Mathematical Packages. A.5 The std_logic_1164 Multivalue Logic System PackageA. 6 Standard Integer Numeric Packages; B VHDL Syntax; B.1 Design File; B.2 Library Unit Declarations; B.3 Declarations and Specifications; B.4 Type Definitions; B.5 Concurrent Statements; B.6 Sequential Statements; B.7 Interfaces and Associations; B.8 Expressions and Names; C Answers to Exercises; References; Index