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  E-mail Message: I thought you might be interested in this item at http://www.worldcat.org/oclc/1026147773 Title: Aceleración de técnicas de ajuste de bloques mediante el procesador Nios II = (Nios II microprocessor-based acceleration of block-matching techniques) Author: Diego González Rodríguez; Guillermo Botella Juan; Universidad Complutense de Madrid. Facultad de Informática. Departamento de Arquitectura de Computadores y Automática Publisher: 2014. OCLC:1026147773

  
  

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Aceleración de técnicas de ajuste de bloques mediante el procesador Nios II = (Nios II microprocessor-based acceleration of block-matching techniques)

Author:	Diego González Rodríguez; Guillermo Botella Juan; Universidad Complutense de Madrid. Facultad de Informática. Departamento de Arquitectura de Computadores y Automática.
Publisher:	2014.
Dissertation:	Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, leída el 16/09/2014.
Edition/Format:	Thesis/dissertation : CD for computer : Thesis/dissertation : Manuscript  Archival Material : English
Rating:	(not yet rated) 0 with reviews - Be the first.
Subjects	Field Programmable Gate Arrays -- Dissertations -- Online. Fpga (hardware) -- Tesis inéditas -- En línea. Microprocesadores -- Tesis inéditas -- En línea. View all subjects
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