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Genre/Form: | Electronic books Conference papers and proceedings Kongress Singapur (2005) Congresses Congrès |
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Additional Physical Format: | Print version: ACSAC 2005 (2005 : Singapore). Advances in computer systems architecture. Berlin ; New York : Springer, 2005 (DLC) 2005934301 (OCoLC)62185932 |
Material Type: | Conference publication, Document, Internet resource |
Document Type: | Internet Resource, Computer File |
All Authors / Contributors: |
Thambipillai Srikanthan; Jingling Xue; Chip-Hong Chang |
ISBN: | 9783540321088 354032108X 3540296433 9783540296430 |
OCLC Number: | 262681870 |
Description: | 1 online resource (xvii, 833 pages) : illustrations |
Contents: | Keynote Address I -- Processor Architecture for Trustworthy Computers -- Session 1A: Energy Efficient and Power Aware Techniques -- Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems -- Energy-Effective Instruction Fetch Unit for Wide Issue Processors -- Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty -- An Innovative Instruction Cache for Embedded Processors -- Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor -- Session 1B: Methodologies and Architectures for Application-Specific Systems -- Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution -- A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC -- Embedded Intelligent Imaging On-Board Small Satellites -- Architectural Enhancements for Color Image and Video Processing on Embedded Systems -- A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output -- Session 2A: Processor Architectures and Microarchitectures -- A Power-Efficient Processor Core for Reactive Embedded Applications -- A Stream Architecture Supporting Multiple Stream Execution Models -- The Challenges of Massive On-Chip Concurrency -- FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit -- Session 2B: High-Reliability and Fault-Tolerant Architectures -- Modularized Redundant Parallel Virtual File System -- Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures -- A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes -- Embedding of Cycles in the Faulty Hypercube -- Session 3A: Compiler and OS for Emerging Architectures -- Improving the Performance of GCC by Exploiting IA-64 Architectural Features -- An Integrated Partitioning and Scheduling Based Branch Decoupling -- A Register Allocation Framework for Banked Register Files with Access Constraints -- Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems -- Irregular Redistribution Scheduling by Partitioning Messages -- Session 3B: Data Value Predictions -- Making Power-Efficient Data Value Predictions -- Speculative Issue Logic -- Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction -- Arithmetic Data Value Speculation -- Exploiting Thread-Level Speculative Parallelism with Software Value Prediction -- Keynote Address II -- Challenges and Opportunities on Multi-core Microprocessor -- Session 4A: Reconfigurable Computing Systems and Polymorphic Architectures -- Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures -- A Switch Wrapper Design for SNA On-Chip-Network -- A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs -- Biological Sequence Analysis with Hidden Markov Models on an FPGA -- FPGAs for Improved Energy Efficiency in Processor Based Systems -- Morphable Structures for Reconfigurable Instruction Set Processors -- Session 4B: Interconnect Networks and Network Interfaces -- Implementation of a Hybrid TCP/IP Offload Engine Prototype -- Matrix-Star Graphs: A New Interconnection Network Based on Matrix Operations -- The Channel Assignment Algorithm on RP(k) Networks -- Extending Address Space of IP Networks with Hierarchical Addressing -- The Star-Pyramid Graph: An Attractive Alternative to the Pyramid -- Building a Terabit Router with XD Networks -- Session 5A: Parallel Architectures and Computation Models -- A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time -- D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters -- Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures -- A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling -- Session 5B: Hardware-Software Partitioning, Verification, and Testing of Complex Architectures -- Minimizing Power in Hardware/Software Partitioning -- Exploring Design Space Using Transaction Level Models -- Increasing Embedding Probabilities of RPRPs in RIN Based BIST -- A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture -- Session 6A: Architectures for Secured Computing -- DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques -- Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor -- Covert Channel Analysis of the Password-Capability System -- Session 6B: Simulation and Performance Evaluation -- Comparing Low-Level Behavior of SPEC CPU and Java Workloads -- Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control -- VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers -- Session 7: Architectures for Emerging Technologies and Applications I -- Analysis of Real-Time Communication System with Queuing Priority -- FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks -- A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems -- Session 8: Memory Systems Hierarchy and Management -- Cache Leakage Management for Multi-programming Workloads -- A Memory Bandwidth Effective Cache Store Miss Policy -- Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance -- Targeted Data Prefetching -- Session 9: Architectures for Emerging Technologies and Applications II -- Area-Time Efficient Systolic Architecture for the DCT -- Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform -- A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures -- Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System. |
Series Title: | Lecture notes in computer science, 3740. |
Other Titles: | ACSAC 2005 |
Responsibility: | Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang (eds.). |
Abstract:
In consultation with the ACSAC Steering Committee, we selected a - member Program Committee. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings.Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions.
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