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CMOS single chip fast frequency hopping synthesizers for wireless multi-gigahertz applications : design methodology, analysis, and implementation

Author: Taoufik Bourdi; İzzet Kale
Publisher: Dordrecht : Springer, ©2007.
Series: Analog circuits and signal processing series.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:
"In this book the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation."--Jacket.
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Additional Physical Format: Online version:
Bourdi, Taoufik.
CMOS single chip fast frequency hopping synthesizers for wireless multi-gigahertz applications.
Dordrecht : Springer, ©2007
(OCoLC)608161596
Online version:
Bourdi, Taoufik.
CMOS single chip fast frequency hopping synthesizers for wireless multi-gigahertz applications.
Dordrecht : Springer, ©2007
(OCoLC)608283045
Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Taoufik Bourdi; İzzet Kale
ISBN: 9781402059278 1402059272
OCLC Number: 124038245
Description: xii, 208 pages : illustrations ; 25 cm.
Contents: Machine derived contents note: Preface ix --
Nomenclature xi --
I INTRODUCTION 1 --
1.1 Introduction 1 --
1,2 Research Contribution 2 --
2 WIRELESS COMMUNICATION SYSTEMS 7 --
2.1 Introduction 7 --
2.2 The WLAN Standards 8 --
2.3 WLAN Transceiver Systems 10 --
2.3.1 The Transmitter 12 --
2.3.2 The Receiver 12 --
2.3.3 The Frequency Synthesizer (Local Oscillator) 13 --
3 PHASE-LOCKED LOOP FREQUENCY SYNTHESIZERS 15 --
3.1 Introduction 15 --
3.2 Phase-Locked Loop Frequency Synthesizer 15 --
3.2.1 Phase-Locked Loop Main Blocks 16 --
3.2.1.1 Phase-Frequency Detector 16 --
3.2.1.2 Charge Pump 17 --
3.2.1.3 Voltage-Controlled Oscillator 18 --
3.2.1.4 Voltage-Controlled Crystal Oscillator 19 --
3.2.1.5 Dividers 19 --
3.3 Phase-Locked Loop Parameters 19 --
3.3.1 Loop Filter Design 20 --
3.4 Noise in Phase-Locked Loops 27 --
3.4. Component Noise Models 29 --
3.4. 1 Reference Oscillator and VCO Phase Noise 30 --
3.4.1.2 Charge Pump Current Noise 30 --
3.4.1.3 Loop Filter Resistor Noise 30 --
3.4.1 4 Main Divider Noise 31 --
3.4.1 ?5 Phase-Frequency Detector Phase Noise 31 --
3.4.1.6 Overall Phase Noise Contribution 32 --
3,5 Fractional-N Synthesizers 34 --
3.5. A-E Modulators in Frequency Synthesizers 36 --
3.5.1 I Fractional-N Case Study 39 --
3.6 RMS Phase Error (m) and Error Vector Magnitude 41 --
3.7 Conclusion 42 --
4 SYSTEM SIMULATION OF A-.-BASED FRACTIONAL-N --
SYNTHESIZERS 45 --
4.1 Introduction 45 --
4.2 Phase-Domain Model 46 --
4.2. 1 A Conslituent Blocks Behavioral Models 50 --
4.2.11 The Reference Oscillator 50 --
4.2.1.2 The A-Z Modulator/Feedback Integer Divider 50 --
4.2.1.3 The VCO 51 --
4,2.1 4 The PFD/CP 52 --
4.2 1.5 The Loop Filter 52 --
4.2.2 Noise Modeling Summary 52 --
4.3 Synthesizer Platform Evaluation 53 --
4.3. Ditherin g Effect 57 --
4. 3.2 Close-to-Integer Operation 60 --
4.3.3 Noise Folding 60 --
43. 4 Effect of Prescaler Divider 62 --
4.4 Conclusion 65 --
5 MULTIMODE A-Z-BASED FRACTIONAL-N FREQUENCY --
SYNTHESIZER 67 --
5.1 Introduction 67 --
5.2 An overview 67 --
5,3 A Multimode Multistandard A --
Based PLL Synthesizer Design 69 --
5.3.1 Design Methodology 69 --
5.4 The A-E Frequency Synthesizer SubBlocks Implementation 71 --
5.4. The Phase-Frequency Detector 71 --
5.4.2 The Charge Pump 73 --
5.4.2.1 Dead-Zone Nonlinearity 76 --
5.4.2.2 Linear Range and Cycle Slipping 78 --
5.4.2.3 DC Offset Current 78 --
5.4.2.4 PFD/CP Transient Simulation 82 --
5.4.3 3.6 GHz Voltage-Controlled Oscillator 85 --
5. 4.4 The Multimodulus Divider 89 --
5.4.4.1 MMD Operation 90 --
5.4. 5 The Fractional Noise Shaping Coder (the A-,E Modulator) 90 --
5'4.5.1 The Digital Accumulator and the First-Order Linear Model 90 --
5.4.5.2 The 30-bit Structural MASH Coder Implementation 92 --
5.4.5.3 The 24-bit Pipelined Adder Design 93 --
5.4.5.4 Error Cancellation Algorithm 95 --
5.4.5.5 Design Issues: Limit Cycle Cancellation in Fractional Mode 97 --
5.4.5.6 Design Issue: Integer Mode and Close-to-Integer Option 99 --
5.5 Measured Performance of the Implemented Synthesizer 102 --
5.6 Summary and Conclusion 107 --
6 IMPROVED PERFORMANCE FRACTIONAL-N FREQUENCY --
SYNTHESIZER 111 --
6.1 Introduction 111 --
6.2 Overview 11l --
6.3 Delta-Sigma-Controlled Adaptive Charge Pump 113 --
6.3.1 PLL Gain and Phase Variations 113 --
6.3.2 Charge Pump System 116 --
6.4 Synthesizer Loop Calibration 117 --
6.5 Process Calibration I/C Slew Rate and RC Time Constant 119 --
6.6 VCO Tuning Gain Calibration 121 --
6,61 VCO Calibration Algorithm Description 121 --
6.6.1.1 AN Values 125 --
6.6.1.2 Summary of Tuning Algorithm Operation 125 --
6.7 Improved VCO Band Switching 126 --
6.8 Experimental Results 127 --
6.9 Comparison with Published Results 128 --
6.10 Conclusion 128 --
7 CONCLUSION AND FURTHER WORK 131 --
7.1 Conclusion 131 --
"7.2 Further Work 132 --
APPENDIX A 135 --
PHASE-FREQUENCY DETECTORS AND CHARGE PUMPS 135 --
1 Phase-Frequency Detectors 135 --
2 Charge Pump 138 --
3 PFD/CP Characteristics 140 --
APPENDIX B 143 --
CONTROLLED OSCILLATORS 143 --
I Reference Oscillators 143 --
1. Voltage-Controlled Crystal Oscillator 143 --
1.2 Temperature-Compensated Crystal Oscillator 145 --
2 Voltage-Controlled Oscillators 146 --
2. Voltage-Controlled Oscillators: Phase Noise Analysis 146 --
2.2 VCO Design Methodology 149 --
2.2.1 VCO Design 150 --
2.2.2 Phase Noise Optimization 153 --
APPENDIX C 157 --
PHASE NOISE 157 --
I Calculation of Global Phase Error From L(f) 157 --
2 Phase Noise and Phase Modulation 159 --
3 RMS Phase Error From Phase Noise 161 --
4 Residual FM 163 --
APPENDIX D 165 --
FREQUENCY DIVIDERS 165 --
I Reference Divider 165 --
1. 1 Synchronous Dividers 165 --
1.2 Asynchronous Reference Frequency Divider 166 --
2 Feedback Divider 168 --
2.1 Specification and Different Architecture Evaluation 168 --
2.1.1 Direct Division versus Prescaler Method 168 --
3 High-Speed CMOS Divider Design 177 --
3. 1 Current-Mode Logic Design: An Overview 1 78 --
4 Implemented CML Gates 183 --
APPENDIX E 187 --
PROGRAMS AND CODES 187 --
I MathcadTM Program used for the Simulations --
of all the Mathcad Figures .187 --
2 MatlabTM Program used for the Simulations --
of the Fractional-N PLL Noise Spectrum 198.
Series Title: Analog circuits and signal processing series.
Responsibility: by Taoufik Bourdi and Izzet Kale.
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Abstract:

In this book, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. The developed techniques in the book can help in  Read more...

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