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Computer architecture : a quantitative approach

Author: John L Hennessy; David A Patterson; Andrea C Arpaci-Dusseau
Publisher: Amsterdam ; Boston : Morgan Kaufmann, 2007.
Edition/Format:   Print book   Computer File : English : 4th edView all editions and formats
Summary:
This new edition of 'Computer Architecture' has been updated throughout to address the historic shift from single-core to multi-core processors.
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Material Type: Internet resource
Document Type: Book, Computer File, Internet Resource
All Authors / Contributors: John L Hennessy; David A Patterson; Andrea C Arpaci-Dusseau
ISBN: 0123704901 9780123704900 0123735904 9780123735904
OCLC Number: 70830951
Description: 1 volume (various pagings) : illustrations ; 24 cm + 1 CD-ROM (4 3/4 in.)
Details: System requirements for accompanying CD-ROM: IBM PC or compatible computer.
Contents: Fundamentals of Computer Design --
Instruction-Level Parallelism and Its Exploitation --
Limits on Instruction-Level Parallelism --
Multiprocessors and Thread-Level Parallelism --
Memory Hierarchy Design --
Storage Systems.
Responsibility: John L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau [and others].
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Abstract:

Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors. This title focuses on this historic shift, providing coverage of  Read more...

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"If Neil Armstrong offers to give you a tour of the lunar module, or Tiger Woods asks you to go play golf with him, you should do it. When Hennessy and Patterson offer to lead you on a tour of where Read more...

 
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<http:\/\/www.worldcat.org\/oclc\/70830951<\/a>> # Computer architecture : a quantitative approach<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Book<\/a>, schema:CreativeWork<\/a> ;\u00A0\u00A0\u00A0\nlibrary:oclcnum<\/a> \"70830951<\/span>\" ;\u00A0\u00A0\u00A0\nlibrary:placeOfPublication<\/a> <http:\/\/dbpedia.org\/resource\/Boston<\/a>> ; # Boston<\/span>\n\u00A0\u00A0\u00A0\nlibrary:placeOfPublication<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Place\/amsterdam<\/a>> ; # Amsterdam<\/span>\n\u00A0\u00A0\u00A0\nlibrary:placeOfPublication<\/a> <http:\/\/id.loc.gov\/vocabulary\/countries\/ne<\/a>> ;\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/id.worldcat.org\/fast\/872026<\/a>> ; # Computer architecture<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/arithmetique_interne_des_ordinateurs<\/a>> ; # Arithm\u00E9tique interne des ordinateurs<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/dewey.info\/class\/004.22\/e22\/<\/a>> ;\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/systemes_enfouis_informatique_conception_et_construction<\/a>> ; # Syst\u00E8mes enfouis (Informatique)--Conception et construction<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/ordinateurs_architecture<\/a>> ; # Ordinateurs--Architecture<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/reseaux_d_ordinateurs<\/a>> ; # R\u00E9seaux d\'ordinateurs<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/multiprocesseurs<\/a>> ; # Multiprocesseurs<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/hierarchie_de_memoires_informatique<\/a>> ; # Hi\u00E9rarchie de m\u00E9moires (Informatique)<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/parallelisme_informatique<\/a>> ; # Parall\u00E9lisme (Informatique)<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/ordinateurs_memoires<\/a>> ; # Ordinateurs--M\u00E9moires<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/arquitetura_e_organizacao_de_computadores<\/a>> ; # Arquitetura e organiza\u00E7\u00E3o de computadores<\/span>\n\u00A0\u00A0\u00A0\nschema:bookEdition<\/a> \"4th ed.<\/span>\" ;\u00A0\u00A0\u00A0\nschema:bookFormat<\/a> bgn:PrintBook<\/a> ;\u00A0\u00A0\u00A0\nschema:contributor<\/a> <http:\/\/viaf.org\/viaf\/2527326<\/a>> ; # David A. Patterson<\/span>\n\u00A0\u00A0\u00A0\nschema:contributor<\/a> <http:\/\/viaf.org\/viaf\/11736873<\/a>> ; # Andrea C. Arpaci-Dusseau<\/span>\n\u00A0\u00A0\u00A0\nschema:creator<\/a> <http:\/\/viaf.org\/viaf\/4986532<\/a>> ; # John L. Hennessy<\/span>\n\u00A0\u00A0\u00A0\nschema:datePublished<\/a> \"2007<\/span>\" ;\u00A0\u00A0\u00A0\nschema:description<\/a> \"Fundamentals of Computer Design -- Instruction-Level Parallelism and Its Exploitation -- Limits on Instruction-Level Parallelism -- Multiprocessors and Thread-Level Parallelism -- Memory Hierarchy Design -- Storage Systems.<\/span>\"@en<\/a> ;\u00A0\u00A0\u00A0\nschema:description<\/a> \"This new edition of \'Computer Architecture\' has been updated throughout to address the historic shift from single-core to multi-core processors.<\/span>\"@en<\/a> ;\u00A0\u00A0\u00A0\nschema:exampleOfWork<\/a> <http:\/\/worldcat.org\/entity\/work\/id\/28485856<\/a>> ;\u00A0\u00A0\u00A0\nschema:inLanguage<\/a> \"en<\/span>\" ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Computer architecture : a quantitative approach<\/span>\"@en<\/a> ;\u00A0\u00A0\u00A0\nschema:productID<\/a> \"70830951<\/span>\" ;\u00A0\u00A0\u00A0\nschema:publication<\/a> <http:\/\/www.worldcat.org\/title\/-\/oclc\/70830951#PublicationEvent\/amsterdam_boston_morgan_kaufmann_2007<\/a>> ;\u00A0\u00A0\u00A0\nschema:publisher<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Agent\/morgan_kaufmann<\/a>> ; # Morgan Kaufmann<\/span>\n\u00A0\u00A0\u00A0\nschema:url<\/a> <http:\/\/catdir.loc.gov\/catdir\/toc\/ecip0618\/2006024358.html<\/a>> ;\u00A0\u00A0\u00A0\nschema:workExample<\/a> <http:\/\/worldcat.org\/isbn\/9780123704900<\/a>> ;\u00A0\u00A0\u00A0\nschema:workExample<\/a> <http:\/\/worldcat.org\/isbn\/9780123735904<\/a>> ;\u00A0\u00A0\u00A0\nwdrs:describedby<\/a> <http:\/\/www.worldcat.org\/title\/-\/oclc\/70830951<\/a>> ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n\n

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<http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/hierarchie_de_memoires_informatique<\/a>> # Hi\u00E9rarchie de m\u00E9moires (Informatique)<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Intangible<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Hi\u00E9rarchie de m\u00E9moires (Informatique)<\/span>\"@fr<\/a> ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
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<http:\/\/experiment.worldcat.org\/entity\/work\/data\/28485856#Topic\/reseaux_d_ordinateurs<\/a>> # R\u00E9seaux d\'ordinateurs<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Intangible<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"R\u00E9seaux d\'ordinateurs<\/span>\"@fr<\/a> ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
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<http:\/\/viaf.org\/viaf\/2527326<\/a>> # David A. Patterson<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Person<\/a> ;\u00A0\u00A0\u00A0\nschema:familyName<\/a> \"Patterson<\/span>\" ;\u00A0\u00A0\u00A0\nschema:givenName<\/a> \"David A.<\/span>\" ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"David A. Patterson<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
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