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Crystal growth and evaluation of silicon for VLSI and ULSI

Author: G Eranna
Publisher: Boca Raton, FL : CRC Press, [2015] 2015
Edition/Format:   eBook : Document : EnglishView all editions and formats
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Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: G Eranna
ISBN: 9781482232820 1482232820
OCLC Number: 930830977
Notes: Visionné le 3 février 2015.
"A Chapman & Hall book."
Description: 1 ressource en ligne (xvii, 141 pages)
Contents: PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPurification of Metallurgical-Grade SiliconUltra-High Pure Silicon for Electronics ApplicationPolycrystalline Silicon Feed for Crystal GrowthSummaryReferencesImportance of Single Crystals for Integrated Circuit FabricationIntroductionCrystal StructuresDifferent Crystal Structures in NatureCubic StructuresDiamond Crystal StructureSilicon Crystal StructureSilicon Crystals and Atomic Packing FactorsCrystal Order and PerfectionCrystal Orientations and PlanesInfluence of Dopants and Impurities in Silicon CrystalsSummaryReferencesDifferent Techniques for Growing Single-Crystal SiliconIntroductionBridgman Crystal Growth TechniqueCzochralski Crystal Growth/Pulling TechniqueCrucible Choice for Molten SiliconChamber Temperature ProfileSeed Selection for Crystal PullingEnvironmental and Ambient Control in the Crystal ChamberCrystal Pull Rate and Seed/Crucible RotationDopant Addition for Growing Doped CrystalsMethods for Continuous Czochralski Crystal GrowthImpurity Segregation between Liquid and Grown Silicon CrystalsCrystal Growth StriationsUse of a Magnetic Field in the Czochralski Growth TechniqueLarge-Area Silicon Crystals for VLSI and ULSI ApplicationsPost-Growth Thermal Gradient and Crystal Cooling after Pull-OutFloat-Zone Crystal Growth TechniqueSeed SelectionEnvironment and Chamber Ambient ControlHeating Mechanisms and RF Coil ShapeCrystal Growth Rate and Seed RotationDopant Distribution in Growing CrystalsImpurity Segregation between Liquid and Grown Silicon CrystalsUse of Magnetic Field for Float-Zone GrowthLarge Area Silicon Crystals and Limitations of Shape and SizeThermal Gradient and Post-Growth Crystal CoolingZone Refining of Single-Crystal SiliconOther Silicon Crystalline Structures and Growth TechniquesSilicon RibbonsSilicon SheetsSilicon Whiskers and FibersSilicon in Circular and Spherical ShapesSilicon Hollow TubesCasting of Polycrystalline Silicon for Photovoltaic ApplicationsSummaryReferencesFrom Silicon Ingots to Silicon WafersIntroductionRadial Resistivity MeasurementsBoule Formation, Identification of Crystal Orientation, and FlatsIngot SlicingMechanical Lapping of Wafer SlicesEdge Profiling of SlicesChemical Etching and Mechanical Damage RemovalChemimechanical Polishing for Planar WafersSurface Roughness and Overall Wafer TopographyMegasonic CleaningFinal Cleaning and InspectionSummaryReferencesEvaluation of Silicon WafersIntroductionAcoustic Laser Probing TechniqueAtomic-Force Microscope Studies on SurfacesAuger Electron Spectroscopic StudiesChemical Staining and Etching TechniquesContactless CharacterizationDeep-Level Transient SpectroscopyDefect Decoration by MetalsElectron Beam and High-Energy Electron Diffraction StudiesFlame Emission SpectrometryFour-Point Probe Technique for Resistivity Measurement and MappingFourier Transform Infrared Spectroscopy Measurements for Impurity IdentificationGas Fusion AnalysisHall MobilityMass Spectra AnalysisMinority Carrier Diffusion Length/Lifetime/Surface PhotovoltageOptical Methods for Impurity EvaluationPhotoluminescence Method for Determining Impurity ConcentrationsGamma-Ray DiffractometryScanning Electron Microscopy for Defect AnalysisScanning Optical MicroscopeSecondary Ion Mass Spectrometer for Impurity DistributionSpreading Resistance and Two-Point Probe Measurement TechniqueStress MeasurementsTransmission Electron Microscopyvan der Pauw Resistivity Measurement Technique for Irregular-Shaped WafersX-Ray Technique for Crystal Perfection and Dislocation DensitySummaryReferencesResistivity and Impurity Concentration Mapping of Silicon WafersIntroductionElectrically Active and Inactive ImpuritiesSurface Mapping and Concentration ContoursSurface Roughness Mapping on a Complete WaferSummaryReferencesImpurities in Silicon WafersEffect of Intentional and Unintentional Impurities and Their Influence on Silicon Devices Intentional Dopant Impurities in Silicon WafersAluminumAntimonyArsenicBoronGalliumPhosphorusUnintentional Dopant Impurities in Silicon WafersCarbonChromiumCopperGermaniumGoldHeliumHydrogenIronNickelNitrogenOxygenTinOther Metallic ImpuritiesSummaryReferencesDefects in Silicon WafersIntroductionImpact of Defects in Silicon Devices and StructuresPoint Defects and VacanciesLine DefectsBulk Defects and VoidsDislocations and Screw DislocationsSwirl DefectsStacking FaultsPrecipitationsSurface Pits/Crystal-Originated ParticlesGrown Vacancies and DefectsThermal DonorsSlips, Cracks, and Shape IrregularitiesStress, Bowing, and WarpageSummaryReferencesSilicon Wafer Preparation for VLSI and ULSI ProcessingIntroductionPurity of Chemicals Used for Silicon ProcessingDegreasing of Silicon WafersRemoval of Metallic and Other ImpuritiesGettering of Metallic ImpuritiesDenuding of Silicon WafersNeutron IrradiationArgon Annealing of WafersHydrogen Annealing of WafersFinal Cleaning, Rinsing, and Wafer DryingSummaryReferencesPacking of Silicon WafersPacking of Fully Processed Blank Silicon WafersStorage of Wafers and Control of Particulate ContaminationStorage of Wafers and Control of Particulate Contamination with Process-Bound WafersSummaryReferencesIndex
Responsibility: Golla Eranna.

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