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Design and simulation of 16 PSK super regenerative receiver

Author: Ashokreddy Kotamreddy
Publisher: [Long Beach, California] : California State University, Long Beach, 2017.
Dissertation: M.S. California State University, Long Beach 2017
Series: California State University, Long Beach.; Master's thesis collection, Department of Electrical Engineering.
Edition/Format:   Thesis/dissertation : Thesis/dissertation : eBook   Computer File : English
Summary:
Abstract: Radio Frequency (RF) communication has developed tremendously over the past two decades. Short-range wireless applications, such as sensor networks, robotics, and home automation, require small area and low power consumption. The receiver must be designed in such a way that it optimizes the area with simple circuitry and minimizes its turn on time to achieve these requirements. This project focuses on  Read more...
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Details

Genre/Form: Academic theses
Material Type: Thesis/dissertation, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Ashokreddy Kotamreddy
ISBN: 9781369706963 1369706960
OCLC Number: 1003043304
Description: 1 online resource (x, 68 pages) : illustrations (some color)
Series Title: California State University, Long Beach.; Master's thesis collection, Department of Electrical Engineering.
Responsibility: by Ashokreddy Kotamreddy.

Abstract:

Abstract: Radio Frequency (RF) communication has developed tremendously over the past two decades. Short-range wireless applications, such as sensor networks, robotics, and home automation, require small area and low power consumption. The receiver must be designed in such a way that it optimizes the area with simple circuitry and minimizes its turn on time to achieve these requirements. This project focuses on designing the 16-PSK (Phase Shift Keying) super regenerative receiver to achieve digital transmission at a higher data rate with low power consumption. The receiver is designed with a Low Noise Amplifier (LNA), Super Regenerative Oscillator (SRO), buffers, RC networks, latches, and flip-flops. The receiver is designed at the 400 MHz frequency with 130nm Complementary Metal Oxide Semiconductor (CMOS) process technology. This receiver can correctly detect the -80 dBm, 4-Mbps signal with a power consumption of 164 [mu]W and Energy Per Bit (EPB) of 0.041nj/b.

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