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Design automation for timing-driven layout synthesis

Author: Sachin S Sapatnekar; Sung-Mo Kang
Publisher: Boston : Kluwer Academic Publishers, ©1993.
Series: Kluwer international series in engineering and computer science, SECS 198.; Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of chip designers would have to increase at the same rate as the level of integration.

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Additional Physical Format: Online version:
Sapatnekar, Sachin S., 1967-
Design automation for timing-driven layout synthesis.
Boston : Kluwer Academic Publishers, ©1993
(OCoLC)645828841
Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Sachin S Sapatnekar; Sung-Mo Kang
ISBN: 0792392817 9780792392811
OCLC Number: 26541403
Description: xx, 269 pages : illustrations ; 25 cm
Contents: List of Figures. 1. Introduction. 2. Delay Estimation. 3. Transistor Sizing Algorithms: Existing Approaches. 4. A Convex Programming Approach to Transistor Sizing. 5. Global Routing Using Zero-One Integer Linear Programming. 6. Timing-Driven CMOS Layout Synthesis. Bibliography. Index.
Series Title: Kluwer international series in engineering and computer science, SECS 198.; Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing.
Responsibility: by Sachin S. Sapatnekar, Sung-Mo (Steve) Kang.
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