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Designing SOCs with Configured Cores : Unleashing the Tensilica Xtensa and Diamond Cores.

Author: Steve Leibson; EBSCOhost.
Publisher: New York : Elsevier, Ipswich : Ebsco Publishing [distributor] Jan. 2009 ;
Series: SOS ebook Collection, Systems on Silicon Ser.
Edition/Format:   Computer file : Online system or service : EnglishView all editions and formats
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Material Type: Online system or service, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Steve Leibson; EBSCOhost.
ISBN: 9780080472454 0080472451
OCLC Number: 847477690
Description: electronic text.
Series Title: SOS ebook Collection, Systems on Silicon Ser.

Abstract:

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Microprocessor cores used for SOC design are the direct descendents of Intel's original 4004 microprocessor. Just as packaged microprocessor ICs vary widely in their attributes, so do microprocessors packaged as IP cores. However, SOC designers still compare and select processor cores the way they previously compared and selected packaged microprocessor ICs. The big problem with this selection method is that it assumes that the laws of the microprocessor universe have remained unchanged for decades. This assumption is no longer valid. Processor cores for SOC designs can be far more plastic than microprocessor ICs for board-level system designs. Shaping these cores for specific applications produces much better processor efficiency and much lower system clock rates. Together, Tensilica's Xtensa and Diamond processor cores constitute a family of software-compatible microprocessors covering an extremely wide performance range from simple control processors, to DSPs, to 3-way superscalar processors. Yet all of these processors use the same software-development tools so that programmers familiar with one processor in the family can easily switch to another. This book emphasizes a processor-centric MPSOC (multiple-processor SOC) design style shaped by the realities of the 21st-century and nanometer silicon. It advocates the assignment of tasks to firmware-controlled processors whenever possible to maximize SOC flexibility, cut power dissipation, reduce the size and number of hand-built logic blocks, shrink the associated verification effort, and minimize the overall design risk.

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