Digital design, with RTL design, VHDL, and Verilog (Book, 2011) [WorldCat.org]
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Digital design, with RTL design, VHDL, and Verilog

Author: Frank Vahid
Publisher: Hoboken (NY) : Wiley, ©2011.
Edition/Format:   Print book : English : 2nd edView all editions and formats
Summary:

Unique with its RTL-early organization, Vahid's text supports instructors wishing to develop strong design skills in their students. The emergence of parallel processing, multicore processors and  Read more...

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Genre/Form: učbeniki za visoke šole
Document Type: Book
All Authors / Contributors: Frank Vahid
ISBN: 9780470531082 0470531088
OCLC Number: 781177064
Description: XVI, 575 str. : ilustr. ; 25 cm
Contents: Preface. To Students About To Study Digital Design. To Instructors of Digital Design. How to Use This Book. RTL-Focused Approach. Traditional Approach with Some Reordering. Traditional Approach. Acknowledgements. About the Cover. About the Author. Reviewers and Evaluators. CHAPTER 1 Introduction. 1.1 Digital Systems in the World Around Us. 1.2 The World of Digital Systems. 1.3 Implementing Digital Systems: Microprocessors versus DigitalCircuits. 1.4 About this Book. 1.5 Exercises. CHAPTER 2 Combinational Logic Design. 2.1 Introduction. 2.2 Switches. 2.3 The CMOS Transistor. 2.4 Boolean Logic Gates Building Blocks for DigitalCircuits. 2.5 Boolean Algebra. 2.6 Representations of Boolean Functions. 2.7 Combinational Logic Design Process. 2.8 More Gates. 2.9 Decoders and Muxes. 2.10 Additional Considerations. 2.11 Combinational Logic Optimizations and Tradeoffs (SeeSection 6.2). 2.12 Combinational Logic Description Using Hardware DescriptionLanguages (See Section 9.2). 2.13 Chapter Summary. 2.14 Exercises. CHAPTER 3 Sequential Logic Design: Controllers. 3.1 Introduction. 3.2 Storing One Bit Flip-Flops. 3.3 Finite-State Machines (FSMs). 3.4 Controller Design. 3.5 More on Flip-Flops and Controllers. 3.6 Sequential Logic Optimizations and Tradeoffs (See Section6.3). 3.7 Sequential Logic Description Using. 3.8 Product Profile Pacemaker. 3.9 Chapter Summary. 3.10 Exercises. CHAPTER 4 Datapath Components. 4.1 Introduction. 4.2 Registers. 4.3 Adders. 4.4 Comparators. 4.5 Multiplier Array-Style. 4.6 Subtractors and Signed Numbers. 4.7 Arithmetic-Logic Units ALUs. 4.8 Shifters. 4.9 Counters and Timers. 4.10 Register Files. 4.11 Datapath Component Tradeoffs (See Section 6.4). 4.12 Datapath Component Description Using Hardware DescriptionLanguages (See Section 9.4). 4.13 Product Profile: An Ultrasound Machine. 4.14 Chapter Summary. 4.15 Exercises. CHAPTER 5 Register-Transfer Level (RTL) Design. 5.1 Introduction. 5.2 High-Level State Machines. 5.3 RTL Design Process. 5.4 More RTL Design. 5.5 Determining Clock Frequency. 5.6 Behavioral-Level Design: C to Gates (Optional). 5.7 Memory Components. 5.8 Queues (FIFOs). 5.9 Multiple Processors. 5.10 Hierarchy A Key Design Concept. 5.11 RTL Design Optimizations and Tradeoffs (See Section6.5). 5.12 RTL Design Using Hardware Description Languages (SeeSection 9.5). 5.13 Product Profile: Cell Phone. 5.14 Chapter Summary. 5.15 Exercises. CHAPTER 6 Optimizations and Tradeoffs. 6.1 Introduction. 6.2 Combinational Logic Optimizations and Tradeoffs. 6.3 Sequential Logic Optimizations and Tradeoffs. 6.4 Datapath Component Tradeoffs. 6.5 RTL Design Optimizations and Tradeoffs. 6.6 More on Optimizations and Tradeoffs. 6.7 Product Profile: Digital Video Player/Recorder. 6.8 Chapter Summary. 6.9 Exercises. CHAPTER 7 Physical Implementation on ICs. 7.1 Introduction. 7.2 Manufactured IC Types. 7.3 Off-the-Shelf Programmable IC Type FPGA. 7.4 Other Off-the-Shelf IC Types. 7.5 IC Tradeoffs, Trends, and Comparisons. 7.6 Product Profile: Giant LED-Based Video. 7.7 Chapter Summary. 7.8 Exercises. CHAPTER 8 Programmable Processors. 8.1 Introduction. 8.2 Basic Architecture. 8.3 A Three-Instruction Programmable Processor. 8.4 A Six-Instruction Programmable Processor. 8.5 Example Assembly and Machine Programs 8.6 Further Extensions to the Programmable Processor. 8.7 Chapter Summary. 8.8 Exercises. CHAPTER 9 Hardware Description Languages. 9.1 Introduction. 9.2 Combinational Logic Description Using Hardware DescriptionLanguages. 9.3 Sequential Logic Description Using Hardware DescriptionLanguages. 9.4 Datapath Component Description. 9.5 RTL Design Using Hardware Description Languages. 9.6 Chapter Summary. 9.7 Exercises. APPENDIX A Boolean Algebras. A.1 Boolean Algebra. A.2 Switching Algebra. A.3 Important Theorems in Boolean Algebra. A.4 Other Examples of Boolean Algebras. A.5 Further Readings. APPENDIX B Additional Topics in Binary NumberSystems. B.1 Introduction. B.2 Real Number Representation. B.3 Fixed Point Arithmetic. B.4 Floating Point Representation. The IEEE 754-1985 Standard. B.5 Exercises. APPENDIX C Extended RTL Design Example. C.1 Introduction. C.2 Designing the Soda Dispenser Controller. C.3 Understanding the Behavior of the Soda Dispenser Controllerand Datapath.
Responsibility: Frank Vahid.

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