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High-level test synthesis of digital VLSI circuits

Author: Mike Tien-Chien Lee
Publisher: Boston : Artech House, ©1997.
Series: Artech House solid-state technology library.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

Explains how HTS is able to explore the synthesis freedom provided at high-level to derive an inherently testable architecture at low or even overhead. This text provides an introduction to HTS and  Read more...

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Additional Physical Format: Online version:
Lee, Mike Tien-Chien.
High-level test synthesis of digital VLSI circuits.
Boston : Artech House, ©1997
(OCoLC)605985753
Document Type: Book
All Authors / Contributors: Mike Tien-Chien Lee
ISBN: 0890069077 9780890069073
OCLC Number: 36143553
Description: xi, 220 pages : illustrations ; 24 cm.
Contents: 1. Introduction --
2. Background --
3. Sequential Depth Reduction During Allocation --
4. Sequential Loop Reduction During Allocation --
5. Testability Synthesis During Scheduling --
6. Conditional Resource Sharing for Testability --
7. State-of-the-Art High-Level Test Synthesis.
Series Title: Artech House solid-state technology library.
Responsibility: Mike Tien-Chien Lee.

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