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Information technology : microprocessor systems -- high-performance synchronous 32-bit bus : MULTIBUS II

Author: Institute of Electrical and Electronics Engineers.; IEEE Computer Society. Technical Committee on Microprocessors and Microcomputers.; American National Standards Institute.; International Organization for Standardization.; International Electrotechnical Commission.
Publisher: New York, NY : Institute of Electrical and Electronics Engineers, 1994.
Series: Institute of Electrical and Electronics Engineers.; IEEE std.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of  Read more...
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Details

Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Institute of Electrical and Electronics Engineers.; IEEE Computer Society. Technical Committee on Microprocessors and Microcomputers.; American National Standards Institute.; International Organization for Standardization.; International Electrotechnical Commission.
ISBN: 1559373687 9781559373685
OCLC Number: 173252373
Notes: "ISO/IEC 10861 : 1994 ; [ANSI/IEEE Std 1296, 1994 Edition]."
"Adopted as an International Standard by the International Organization for Standardization and by the International Electrotechnical Commission."
Description: 1 online resource (viii, 130 pages) : illustrations
Series Title: Institute of Electrical and Electronics Engineers.; IEEE std.
Other Titles: ANSI/IEEE Std 1296-1994, ISO/IEC 10861.
ISO/IEC 10861 : 1994.
ANSI/IEEE Std 1296, 1994 Edition.
Microprocessor systems -- high-performance synchronous 32-bit bus : MULTIBUS II
MULTIBUS II
Responsibility: sponsor, Technical Committee on Microprocessors and Micrcomputers of the IEEE Computer Society.

Abstract:

The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective, high-performance VLSI for the bus interface. Memory, I/O, message, and geographic address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilitze the bus at its highest performance 32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered.

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