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Genre/Form: | Electronic books |
---|---|
Additional Physical Format: | Print version: Leakage in nanometer CMOS technologies. New York : Springer, 2006 (DLC) 2005932184 (OCoLC)62510295 |
Material Type: | Document, Internet resource |
Document Type: | Internet Resource, Computer File |
All Authors / Contributors: |
Siva G Narendra; Anantha P Chandrakasan |
ISBN: | 9780387281339 0387281339 0387257373 9780387257372 6610616582 9786610616589 |
OCLC Number: | 209908125 |
Description: | 1 online resource (x, 307 pages) : illustrations |
Contents: | Taxonomy of leakage : sources, impact, and solutions -- Leakage dependence on input vector / Siva Narendra [and others] -- Power gating and dynamic voltage scaling / Benton Calhoun, James Kao, and Anantha Chandrakasan -- Methodologies for power gating / Kimiyoshi Usami and Takayasu Sakurai -- Body biasing / Tadahiro Kuroda and Takayasu Sakurai -- Process variation and adaptive design / Siva Narendra [and others] -- Memory leakage reduction / Takayuki Kawahara and Kiyoo Itoh -- Active leakage reduction and multi-performance devices / Siva Narendra [and others] -- Impact of leakage power and variation on testing / Ali Keshavarzi and Kaushik Roy -- Case study : leakage reduction in Hitachi/Renesas microprocessors / Masayuki Miyazaki, Hiroyuki Mizuno, and Takayuki Kawahara -- Case study : leakage reduction in the Intel Xscale microprocessor / Lawrence Clark -- Transistor design to reduce leakage / Sagar Suthram, Siva Narendra, and Scott Thompson. |
Series Title: | Series on integrated circuits and systems. |
Responsibility: | [ed. by] Siva G. Narendra, Anantha Chandrakasan. |
More information: |
Abstract:
Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles.
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