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Leakage in nanometer CMOS technologies

Author: Siva G Narendra; Anantha P Chandrakasan
Publisher: New York : Springer, 2006.
Series: Series on integrated circuits and systems.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Leakage in nanometer CMOS technologies.
New York : Springer, 2006
(DLC) 2005932184
(OCoLC)62510295
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Siva G Narendra; Anantha P Chandrakasan
ISBN: 9780387281339 0387281339 0387257373 9780387257372 6610616582 9786610616589
OCLC Number: 209908125
Description: 1 online resource (x, 307 pages) : illustrations
Contents: Taxonomy of leakage : sources, impact, and solutions --
Leakage dependence on input vector / Siva Narendra [and others] --
Power gating and dynamic voltage scaling / Benton Calhoun, James Kao, and Anantha Chandrakasan --
Methodologies for power gating / Kimiyoshi Usami and Takayasu Sakurai --
Body biasing / Tadahiro Kuroda and Takayasu Sakurai --
Process variation and adaptive design / Siva Narendra [and others] --
Memory leakage reduction / Takayuki Kawahara and Kiyoo Itoh --
Active leakage reduction and multi-performance devices / Siva Narendra [and others] --
Impact of leakage power and variation on testing / Ali Keshavarzi and Kaushik Roy --
Case study : leakage reduction in Hitachi/Renesas microprocessors / Masayuki Miyazaki, Hiroyuki Mizuno, and Takayuki Kawahara --
Case study : leakage reduction in the Intel Xscale microprocessor / Lawrence Clark --
Transistor design to reduce leakage / Sagar Suthram, Siva Narendra, and Scott Thompson.
Series Title: Series on integrated circuits and systems.
Responsibility: [ed. by] Siva G. Narendra, Anantha Chandrakasan.
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Abstract:

Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from  Read more...

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Primary Entity<\/h3>\n
<http:\/\/www.worldcat.org\/oclc\/209908125<\/a>> # Leakage in nanometer CMOS technologies<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:MediaObject<\/a>, schema:CreativeWork<\/a>, schema:Book<\/a> ;\u00A0\u00A0\u00A0\nlibrary:oclcnum<\/a> \"209908125<\/span>\" ;\u00A0\u00A0\u00A0\nlibrary:placeOfPublication<\/a> <http:\/\/id.loc.gov\/vocabulary\/countries\/nyu<\/a>> ;\u00A0\u00A0\u00A0\nlibrary:placeOfPublication<\/a> <http:\/\/dbpedia.org\/resource\/New_York_City<\/a>> ; # New York<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/905974541#Topic\/metal_oxide_semiconductors_complementary_design_and_construction<\/a>> ; # Metal oxide semiconductors, Complementary--Design and construction<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/id.worldcat.org\/fast\/975545<\/a>> ; # Integrated circuits--Design and construction<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/905974541#Topic\/ingenierie<\/a>> ; # Ing\u00E9nierie<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/dewey.info\/class\/621.38412\/e22\/<\/a>> ;\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/905974541#Topic\/integrated_circuits_design_and_construction<\/a>> ; # Integrated circuits--Design and construction<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/id.loc.gov\/authorities\/subjects\/sh85067118<\/a>> ; # Integrated circuits--Design and construction<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/905974541#Topic\/technology_&_engineering_mobile_&_wireless_communications<\/a>> ; # TECHNOLOGY & ENGINEERING--Mobile & Wireless Communications<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/id.worldcat.org\/fast\/1017641<\/a>> ; # Metal oxide semiconductors, Complementary--Design and construction<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/905974541#Topic\/technology_&_engineering_radio<\/a>> ; # TECHNOLOGY & ENGINEERING--Radio<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/905974541#Topic\/electric_leakage_prevention<\/a>> ; # Electric leakage--Prevention<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/id.loc.gov\/authorities\/subjects\/sh2008107701<\/a>> ; # Metal oxide semiconductors, Complementary--Design and construction<\/span>\n\u00A0\u00A0\u00A0\nschema:bookFormat<\/a> schema:EBook<\/a> ;\u00A0\u00A0\u00A0\nschema:contributor<\/a> <http:\/\/viaf.org\/viaf\/278885474<\/a>> ; # Anantha P. Chandrakasan<\/span>\n\u00A0\u00A0\u00A0\nschema:contributor<\/a> <http:\/\/viaf.org\/viaf\/63529127<\/a>> ; # Siva Gurusami Narendra<\/span>\n\u00A0\u00A0\u00A0\nschema:datePublished<\/a> \"2006<\/span>\" ;\u00A0\u00A0\u00A0\nschema:description<\/a> \"Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. 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<http:\/\/viaf.org\/viaf\/278885474<\/a>> # Anantha P. Chandrakasan<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Person<\/a> ;\u00A0\u00A0\u00A0\nschema:familyName<\/a> \"Chandrakasan<\/span>\" ;\u00A0\u00A0\u00A0\nschema:givenName<\/a> \"Anantha P.<\/span>\" ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Anantha P. Chandrakasan<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/viaf.org\/viaf\/63529127<\/a>> # Siva Gurusami Narendra<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Person<\/a> ;\u00A0\u00A0\u00A0\nschema:birthDate<\/a> \"1971<\/span>\" ;\u00A0\u00A0\u00A0\nschema:familyName<\/a> \"Narendra<\/span>\" ;\u00A0\u00A0\u00A0\nschema:givenName<\/a> \"Siva Gurusami<\/span>\" ;\u00A0\u00A0\u00A0\nschema:givenName<\/a> \"Siva G.<\/span>\" ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Siva Gurusami Narendra<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
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