Leakage in nanometer CMOS technologies (Book, 2006) [WorldCat.org]
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Leakage in nanometer CMOS technologies

Author: Siva G Narendra; Anantha P Chandrakasan
Publisher: New York : Springer, 2006.
Series: Series on integrated circuits and systems.
Edition/Format:   Print book : EnglishView all editions and formats

Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from  Read more...


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Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Siva G Narendra; Anantha P Chandrakasan
ISBN: 0387257373 0387281339 9780387257372 9780387281339
OCLC Number: 62510295
Description: x, 307 pages : illustrations ; 24 cm
Contents: Taxonomy of leakage : sources, impact, and solutions --
Leakage dependence on input vector / Siva Narendra [and others] --
Power gating and dynamic voltage scaling / Benton Calhoun, James Kao, and Anantha Chandrakasan --
Methodologies for power gating / Kimiyoshi Usami and Takayasu Sakurai --
Body biasing / Tadahiro Kuroda and Takayasu Sakurai --
Process variation and adaptive design / Siva Narendra [and others] --
Memory leakage reduction / Takayuki Kawahara and Kiyoo Itoh --
Active leakage reduction and multi-performance devices / Siva Narendra [and others] --
Impact of leakage power and variation on testing / Ali Keshavarzi and Kaushik Roy --
Case study : leakage reduction in Hitachi/Renesas microprocessors / Masayuki Miyazaki, Hiroyuki Mizuno, and Takayuki Kawahara --
Case study : leakage reduction in the Intel Xscale microprocessor / Lawrence Clark --
Transistor design to reduce leakage / Sagar Suthram, Siva Narendra, and Scott Thompson.
Series Title: Series on integrated circuits and systems.
Responsibility: [ed. by] Siva G. Narendra, Anantha Chandrakasan.
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