Logic synthesis and verification algorithms (Book, 2006) [WorldCat.org]
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Logic synthesis and verification algorithms

Author: Gary D Hachtel; Fabio Somenzi
Publisher: New York : Springer, cop. 2006.
Edition/Format:   Print book : EnglishView all editions and formats

This book blends mathematical foundations and algorithmic developments with circuit design issues. Through the study of optimal two-level and multilevel combinational circuit design, the reader is  Read more...


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Document Type: Book
All Authors / Contributors: Gary D Hachtel; Fabio Somenzi
ISBN: 0387310045 9780387310046
OCLC Number: 438831748
Description: XXXII, 564 str. : ilustr. ; 26 cm
Contents: I: Introduction.1. Introduction.2. A Quick Tour of Logic Synthesis with the Help of a Simple Example.- II: Two Level Logic Synthesis. 3. Boolean Algebras. 4. Synthesis of Two-Level Circuits. 5. Heuristic Minimization of Two-Level Circuits. 6. Binary Decision Diagrams (BDDs).- III: Models of Sequential Systems. 7. Models of Sequential Systems. 8. Synthesis and Verification of Finite State Machines. 9. Finite Automata. IV: Multilevel Logic Synthesis. 10. Multi-Level Logic Synthesis. 11. Multi-Level Minimization. 12. Automatic Test Generation for Combinational Circuits. 13. Technology Mapping. A. ASCII Codes. B. Supplementary Problems.- Bibliography.- Index.
Responsibility: by Gary D. Hachtel, Fabio Somenzi.


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