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Logic-timing simulation and the degradation delay model

Author: Manuel J Bellido; Jorge Juan Chico; Manuel Valencia
Publisher: London : Imperial College Press, ©2006.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Bellido, Manuel J., 1964-
Logic-timing simulation and the degradation delay model.
London : Imperial College Press, ©2006
(OCoLC)64790367
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Manuel J Bellido; Jorge Juan Chico; Manuel Valencia
ISBN: 1860945899 9781860945892 1860947360 9781860947360
OCLC Number: 191818232
Description: 1 online resource (xvii, 267 pages) : illustrations
Contents: Machine generated contents note: 1. Fundamentals of timing simulation --
2. Delay models : evolution and trends --
3. Degradation and inertial effects --
4. CMOS inverter degradation delay model --
5. Gate-level DDM --
6. Logic level simulator design and implementation --
7. DDM simulation results.
Responsibility: Manuel J. Bellido, Jorge Juan, Manuel Valencia.
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Abstract:

Provides the reader with a background in the field of logic-timing simulation and delay modeling. This book includes detailed information on the challenges of logic-timing simulation, applications,  Read more...

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