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A new family of CMOS cascode-free amplifiers with high energy-efficiency and improved gain

Author: Ricardo Filipe Sereno Póvoa; João Carlos da Palma Goes; Nuno Cavaco Gomes Horta
Publisher: Cham : Springer, [2018] ©2019
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
This book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of single-stage cascode-free amplifiers, with proper design, optimization, fabrication and experimental evaluation. The authors describe several topologies, using the UMC 130 nm CMOS technology node with standard-VT devices, for  Read more...
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Genre/Form: Electronic books
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Ricardo Filipe Sereno Póvoa; João Carlos da Palma Goes; Nuno Cavaco Gomes Horta
ISBN: 9783319952079 3319952072
OCLC Number: 1048428933
Description: 1 online resource : illustrations (some color)
Contents: Intro; Preface; Acknowledgments; Contents; List of Abbreviations; List of Symbols; Chapter 1: Introduction; References; Chapter 2: Background and State of the Art; 2.1 Background and Initial Considerations; 2.2 Overview on Amplifiers; 2.2.1 Operational Amplifiers; 2.2.2 Single-Stage Amplifiers; 2.3 Performance Metrics of Amplifiers; 2.3.1 Gain and Gain-Bandwidth Product; 2.3.2 Figure of Merit; 2.3.3 Noise; 2.3.4 Common-Mode Rejection Ratio; 2.3.5 Power Supply Rejection Ratio; 2.3.6 Slew Rate; 2.3.7 Settling Time; 2.3.8 Offset Voltage; 2.3.9 Output Voltage Swing 2.3.10 Stability and Frequency Compensation2.4 Operational Transconductance Amplifiers; 2.5 The Cascode Amplifier Topologies; 2.5.1 Basic Cascode Stages; 2.5.2 Telescopic-Cascode Amplifier; 2.5.3 Mirrored-Cascode Amplifier; 2.5.4 Folded-Cascode Amplifier; 2.5.5 Gain Enhancement Techniques for the Cascode Architectures; 2.6 The Recycling Folded-Cascode Amplifier; 2.7 Dynamic CMOS Amplifiers; 2.8 Summary; References; Chapter 3: Proposed Family of CMOS Amplifiers; 3.1 Voltage-Combiner Structure; 3.2 Voltage-Combiner-Biased OTA; 3.3 Voltage-Combiner-Biased OTA with Current Starving 3.4 Folded Voltage-Combiner-Biased OTA3.5 Dynamic Voltage-Combiner-Biased OTA; 3.6 Noise Modeling; 3.6.1 Noise Definition; 3.6.2 Noise Types; 3.6.3 Generic Modeling; 3.6.4 Voltage-Combiner Noise Modeling; 3.7 Summary; References; Chapter 4: Design Optimization and Results; 4.1 Optimization Framework; 4.2 Voltage-Combiner Biased OTA; 4.3 Voltage-Combiner Biased OTA with Current Starving; 4.4 Folded Voltage-Combiner Biased OTA; 4.5 Dynamic Voltage-Combiner Biased OTA; 4.6 EDA Techniques in Organic TFT Technologies; 4.6.1 Context of Organic Technology; 4.6.2 Optimization Setup 4.6.3 Optimization Results4.6.4 Yield Optimization Process; 4.7 Summary; References; Chapter 5: Integrated Prototypes and Experimental Evaluation; 5.1 Test Printed Circuit Board; 5.2 Voltage-Combiner-Biased OTA; 5.3 Voltage-Combiner-Biased OTA with Current Starving; 5.4 Summary; References; Chapter 6: Conclusions and Future Prospects; Biographies; Index
Responsibility: Ricardo Felipe Sereno Póvoa, João Carlos da Palma Goes, Nuno Cavaco Gomes Horta.

Abstract:

This book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of  Read more...

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