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A primer on memory consistency and cache coherence

Author: Vijay Nagarajan; Daniel J Sorin; Mark D Hill; David Allen Wood
Publisher: [San Rafael, California] : Morgan & Claypool, [2020]
Series: Synthesis lectures in computer architecture, #49.
Edition/Format:   eBook : Document : English : Second editionView all editions and formats
Summary:
Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Vijay Nagarajan; Daniel J Sorin; Mark D Hill; David Allen Wood
ISBN: 1681737108 9781681737102
OCLC Number: 1142818522
Description: 1 online resource (xx, 274 pages) : illustrations.
Contents: 1. Introduction to consistency and coherence --
1.1. Consistency (a.k.a., memory consistency, memory consistency model, or memory model) --
1.2. Coherence (a.k.a., cache coherence) --
1.3. Consistency and coherence for heterogeneous systems --
1.4. Specifying and validating memory consistency models and cache coherence --
1.5. A consistency and coherence quiz --
1.6. What this primer does not do --
1.7. References 2. Coherence basics --
2.1. Baseline system model --
2.2. The problem : how incoherence could possibly occur --
2.3. The cache coherence interface --
2.4. (Consistency-agnostic) coherence invariants --
2.5. References 3. Memory consistency motivation and sequential consistency --
3.1. Problems with shared memory behavior --
3.2. What is a memory consistency model? --
3.3. Consistency vs. coherence --
3.4. Basic idea of sequential consistency (SC) --
3.5. A little SC formalism --
3.6. Naive SC implementations --
3.7. A basic SC implementation with cache coherence --
3.8. Optimized SC implementations with cache coherence --
3.9. Atomic operations with SC --
3.10. Putting it all together : MIPS R10000 --
3.11. Further reading regarding SC --
3.12. References 4. Total store order and the x86 memory model --
4.1. Motivation for TSO/x86 --
4.2. Basic idea of TSO/x86 --
4.3. A little TSO/x86 formalism --
4.4. Implementing TSO/x86 --
4.5. Further reading regarding TSO --
4.6. Comparing SC and TSO --
4.7. References 5. Relaxed memory consistency --
5.1. Motivation --
5.2. An example relaxed consistency model (XC) --
5.3. Implementing XC --
5.4. Sequential consistency for data-race-free programs --
5.5. Some relaxed model concepts --
5.6. Relaxed memory model case studies --
5.7. Further reading and commercial relaxed memory models --
5.8. Comparing memory models --
5.9. High-level language models --
5.10. References 6. Coherence protocols --
6.1. The big picture --
6.2. Specifying coherence protocols --
6.3. Example of a simple coherence protocol --
6.4. Overview of coherence protocol design space --
6.5. References 7. Snooping coherence protocols --
7.1. Introduction to snooping --
7.2. Baseline snooping protocol --
7.3. Adding the exclusive state --
7.4. Adding the owned state --
7.5. Non-atomic bus --
7.6. Optimizations to the bus interconnection network --
7.7. Case studies --
7.8. Discussion and the future of snooping --
7.9. References 8. Directory coherence protocols --
8.1. Introduction to directory protocols --
8.2. Baseline directory system --
8.3. Adding the exclusive state --
8.4. Adding the owned state --
8.5. Representing directory state --
8.6. Directory organization --
8.7. Performance and scalability optimizations --
8.8. Case studies --
8.9. Discussion and the future of directory protocols --
8.10. References 9. Advanced topics in coherence --
9.1. System models --
9.2. Performance optimizations --
9.3. Maintaining liveness --
9.4. Token coherence --
9.5. The future of coherence --
9.6. References 10. Consistency and coherence for heterogeneous systems --
10.1. GPU consistency and coherence --
10.2. More heterogeneity than just GPUs --
10.3. Further reading --
10.4. References 11. Specifying and validating memory consistency models and cache coherence --
11.1. Specification --
11.2. Exploring the behavior of memory consistency models --
11.3. Validating implementations --
11.4. History and further reading --
11.5. References.
Series Title: Synthesis lectures in computer architecture, #49.
Responsibility: Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood.

Abstract:

Provides readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. The book presents both  Read more...

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Sorin<\/span>\n\u00A0\u00A0\u00A0\nschema:contributor<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Person\/wood_david_allen<\/a>> ; # David Allen Wood<\/span>\n\u00A0\u00A0\u00A0\nschema:contributor<\/a> <http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Person\/hill_mark_d_mark_donald<\/a>> ; # Mark Donald Hill<\/span>\n\u00A0\u00A0\u00A0\nschema:datePublished<\/a> \"2020<\/span>\" ;\u00A0\u00A0\u00A0\nschema:description<\/a> \"Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.<\/span>\"@en<\/a> ;\u00A0\u00A0\u00A0\nschema:description<\/a> \"1. Introduction to consistency and coherence -- 1.1. Consistency (a.k.a., memory consistency, memory consistency model, or memory model) -- 1.2. Coherence (a.k.a., cache coherence) -- 1.3. Consistency and coherence for heterogeneous systems -- 1.4. Specifying and validating memory consistency models and cache coherence -- 1.5. A consistency and coherence quiz -- 1.6. What this primer does not do -- 1.7. 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Related Entities<\/h3>\n
<http:\/\/dewey.info\/class\/005.43\/e22\/<\/a>>\u00A0\u00A0\u00A0\u00A0a \nschema:Intangible<\/a> ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
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<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Person\/hill_mark_d_mark_donald<\/a>> # Mark Donald Hill<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Person<\/a> ;\u00A0\u00A0\u00A0\nschema:familyName<\/a> \"Hill<\/span>\" ;\u00A0\u00A0\u00A0\nschema:givenName<\/a> \"Mark Donald<\/span>\" ;\u00A0\u00A0\u00A0\nschema:givenName<\/a> \"Mark D.<\/span>\" ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Mark Donald Hill<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Person\/nagarajan_vijay<\/a>> # Vijay Nagarajan<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Person<\/a> ;\u00A0\u00A0\u00A0\nschema:familyName<\/a> \"Nagarajan<\/span>\" ;\u00A0\u00A0\u00A0\nschema:givenName<\/a> \"Vijay<\/span>\" ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Vijay Nagarajan<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Person\/sorin_daniel_j<\/a>> # Daniel J. Sorin<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Person<\/a> ;\u00A0\u00A0\u00A0\nschema:familyName<\/a> \"Sorin<\/span>\" ;\u00A0\u00A0\u00A0\nschema:givenName<\/a> \"Daniel J.<\/span>\" ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Daniel J. Sorin<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Person\/wood_david_allen<\/a>> # David Allen Wood<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Person<\/a> ;\u00A0\u00A0\u00A0\nschema:familyName<\/a> \"Wood<\/span>\" ;\u00A0\u00A0\u00A0\nschema:givenName<\/a> \"David Allen<\/span>\" ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"David Allen Wood<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Series\/synthesis_lectures_in_computer_architecture<\/a>> # Synthesis lectures in computer architecture ;<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nbgn:PublicationSeries<\/a> ;\u00A0\u00A0\u00A0\nschema:hasPart<\/a> <http:\/\/www.worldcat.org\/oclc\/1142818522<\/a>> ; # A primer on memory consistency and cache coherence<\/span>\n\u00A0\u00A0\u00A0\nschema:name<\/a> \"Synthesis lectures in computer architecture ;<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/accelerators<\/a>> # accelerators<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"accelerators<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/cache_coherence<\/a>> # cache coherence<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"cache coherence<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/computer_architecture<\/a>> # computer architecture<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"computer architecture<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/gpu<\/a>> # GPU<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"GPU<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/heterogeneous_architecture<\/a>> # heterogeneous architecture<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"heterogeneous architecture<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/memory_consistency<\/a>> # memory consistency<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"memory consistency<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/memory_systems<\/a>> # memory systems<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"memory systems<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/multicore_processor<\/a>> # multicore processor<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"multicore processor<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/semantics<\/a>> # semantics<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"semantics<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/shared_memory<\/a>> # shared memory<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"shared memory<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Thing\/verification<\/a>> # verification<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Thing<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"verification<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Topic\/cache_memory<\/a>> # Cache memory<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Intangible<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Cache memory<\/span>\"@en<\/a> ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
<http:\/\/experiment.worldcat.org\/entity\/work\/data\/903299225#Topic\/memory_management_computer_science<\/a>> # Memory management (Computer science)<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:Intangible<\/a> ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Memory management (Computer science)<\/span>\"@en<\/a> ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
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<http:\/\/worldcat.org\/entity\/work\/data\/903299225#CreativeWork\/<\/a>>\u00A0\u00A0\u00A0\u00A0a \nschema:CreativeWork<\/a> ;\u00A0\u00A0\u00A0\nschema:description<\/a> \"Print version:<\/span>\" ;\u00A0\u00A0\u00A0\nschema:isSimilarTo<\/a> <http:\/\/www.worldcat.org\/oclc\/1142818522<\/a>> ; # A primer on memory consistency and cache coherence<\/span>\n\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n
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<http:\/\/worldcat.org\/issn\/1935-3243<\/a>> # Synthesis lectures on computer architecture,<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nbgn:PublicationSeries<\/a> ;\u00A0\u00A0\u00A0\nschema:hasPart<\/a> <http:\/\/www.worldcat.org\/oclc\/1142818522<\/a>> ; # A primer on memory consistency and cache coherence<\/span>\n\u00A0\u00A0\u00A0\nschema:issn<\/a> \"1935-3243<\/span>\" ;\u00A0\u00A0\u00A0\nschema:name<\/a> \"Synthesis lectures on computer architecture,<\/span>\" ;\u00A0\u00A0\u00A0\u00A0.\n\n\n<\/div>\n