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A probabilistic model of memory acceses for efficient CPU caching

Author: Subhasis Das; William J Dally; Tor M Aamodt; Mendel Rosenblum; Stanford University. Department of Electrical Engineering.
Publisher: 2016.
Dissertation: Ph. D. Stanford University 2016
Edition/Format:   Thesis/dissertation : Document : Thesis/dissertation : eBook   Computer File : English
Summary:
The memory hierarchy in a modern processor -- the main memory and different cache levels, consumes about half of the full system energy. We reduce the memory hierarchy energy by three methods: a) reducing main memory accesses by building better last level cache replacement policies, b) reducing wire energy in LLCs by doing intelligent placement and movement of data, and, c) reducing L1 access energy by performing  Read more...
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Details

Genre/Form: Academic theses
Material Type: Document, Thesis/dissertation, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Subhasis Das; William J Dally; Tor M Aamodt; Mendel Rosenblum; Stanford University. Department of Electrical Engineering.
OCLC Number: 944735043
Notes: Submitted to the Department of Electrical Engineering.
Description: 1 online resource
Responsibility: Subhasis Das.

Abstract:

The memory hierarchy in a modern processor -- the main memory and different cache levels, consumes about half of the full system energy. We reduce the memory hierarchy energy by three methods: a) reducing main memory accesses by building better last level cache replacement policies, b) reducing wire energy in LLCs by doing intelligent placement and movement of data, and, c) reducing L1 access energy by performing accurate assignment of cache ways to memory access instructions. To design these policies, we propose a new model for program access patterns: the IID Sequence Model (ISM), which uses the reuse distance distributions of different cache lines. We show that a) our proposed Probabilistic Replacement Policy (PRP) reduces LLC misses by 6.6% over state-of-the-art replacement policies such as SHiP [91], b) Sub-Level Insertion Policy (SLIP), which places and moves cache lines according to their reuse distance distribution, reduces L2 energy by 35% and L3 energy by 22%, and, c) Cache Way Assignment (CWA) reduces L1D cache energy consumption by 14% by reducing way mispredictions.

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