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Sequential Logic Synthesis

Author: Pranav Ashar; Srinivas Devadas; A Richard Newton
Publisher: Boston, MA : Springer US, 1992.
Series: Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing ;, 162.
Edition/Format:   eBook : Document : EnglishView all editions and formats
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2 Input Encoding Targeting Two-Level Logic . 3 Satisfying Encoding Constraints . 3 Row-Based Constraint Satisfaction . 4 Constraint Satisfaction Using Dichotomies . 3 Heuristics to Minimize the  Read more...

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Genre/Form: Electronic books
Additional Physical Format: Print version:
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Pranav Ashar; Srinivas Devadas; A Richard Newton
ISBN: 9781461536284 1461536286
OCLC Number: 851829525
Description: 1 online resource (xx, 225 pages).
Contents: Acknowledgments --
1 Introduction --
1.1 Computer-Aided VLSI Design --
1.2 The Synthesis Pipeline --
1.3 Sequential Logic Synthesis --
1.4 Early Work in Sequential Logic Synthesis --
1.5 Recent Developments --
1.6 Organization of the Book --
2 Basic Definitions and Concepts --
2.1 Two-Valued Logic --
2.2 Multiple-Valued Logic --
2.3 Multilevel Logic --
2.4 Multiple-Valued Input, Multilevel Logic --
2.5 Finite Automata --
3 Encoding of Symbolic Inputs --
3.1 Introduction --
3.2 Input Encoding Targeting Two-Level Logic --
3.3 Satisfying Encoding Constraints --
3.4 Input Encoding Targeting Multilevel Logic --
3.5 Conclusion --
4 Encoding of Symbolic Outputs --
4.1 Heuristic Output Encoding Targeting Two-Level Logic --
4.2 Exact Output Encoding Targeting Two-Level Logic --
4.3 Symbolic Output Don't Cares --
4.4 Output Encoding for Multilevel Logic --
4.5Conclusion --
5 State Encoding --
5.1 Heuristic State Encoding Targeting Two-Level Logic --
5.2 Exact State Encoding for Two-Level Logic --
5.3 Symbolic Next State Don't Cares --
5.4 State Encoding for Multilevel Logic --
5.5 Conclusion --
6 Finite State Machine Decomposition --
6.1 Introduction --
6.2 Definitions for Decomposition --
6.3 Preserved Covers and Partitions --
6.4 General Decomposition Using Factors --
6.5 Exact Decomposition Procedure for a Two-Way General Topology --
6.6 Targeting Arbitrary Topologies --
6.8 Relationship to State Assignment --
6.9 Experimental Results --
6.10 Conclusion --
7 Sequential Don't Cares --
7.1 Introduction --
7.2 State Minimization --
7.3 Input Don't Care Sequences --
7.4 Output Don't Cares to Minimize States --
7.5 Single Machine Optimization at the Logic Level --
7.6 Interconnected Machine Optimization at the Logic Level --
7.7 Conclusion --
8 Conclusions and Directions for Future Work --
8.1 Alternate Representations --
8.2 Optimization at the Logic Level --
8.3 Don't Cares and Testability --
8.4 Exploiting Register-Transfer Level Information --
8.5 Sequential Logic Synthesis Systems.
Series Title: Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing ;, 162.
Responsibility: by Pranav Ashar, Srinivas Devadas, A. Richard Newton.

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