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System-on-chip for real-time applications

Author: Wael Badawy; Graham Jullien
Publisher: Boston : Kluwer Academic Publishers, 2003.
Series: Kluwer international series in engineering and computer science, SECS 711.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

System-on-Chip for Real-Time Applications will be of interest to engineers, both in industry and academia, working in the area of SoC VLSI design and application.

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Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Wael Badawy; Graham Jullien
ISBN: 1402072546 9781402072543
OCLC Number: 50478525
Description: xii, 456 pages : illustrations ; 25 cm.
Contents: Ch. 1. Introduction --
System on Chip: The Challenge and Opportunities / Wael Badawy --
Electronic Product Innovation Direct Mapped Signal Processing SoC Cores / John V. McCanny --
System-On-Chip Implementation of Signal Processors / Earl E. Swartzlander, Jr. --
Ch. 2. Design Reuse --
Methodologies and Strategies for Effective Design-Reuse / Ludovic Loiseau and Yvon Savaria --
A VHDL/SystemC Comparison in Handling Design Reuse / Luc Charest and El Mostapha Aboulhamid --
Aspect Partitioning for Hardware Verification Reuse / Sebastien Regimbal, Jean-FrancoisLemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid and Andre Baron --
Reconfigurable Combinatorial Accelerators for Real Time Processing / I. Skliarova and A. B. Ferrari --
Tuning Methodologies for Parameterized Systems Design / Guiseppe Ascia, Vincenzo Catania and Maurizio Palesi --
Ch. 3. Test and Verification --
Formal Verifications of Systems on Chips: Current and Future Directions / Khaled M. Elleithy --
A Practical Approach to the Formal Verification of SoC's with Symbolic Model-Checking / Emil Dumitrescu --
High Performance Verification Solutions for SOC Designs / Makarand Joshi and Ashok Kumar --
Novel Test Methodologies for SoC/IP Design: Implementation and Comparison / L. Hong, M. Nahvi, R. Fung, A. Ivanov and R. Saleh --
Ch. 4. Modeling --
SOC Modeling and Simulation Based on Java / Henry Fu and Richard F. Hobson --
RTOS Modeling Using SystemC / Mohamed Abd El-Salam, Ashraf Salem and Gamal Aly --
Modeling, Synthesis and Implementation of Communicating Hierarchical FSM / Valery Sklyarov --
A Modeling Method for Reconfigurable Architectures / Lilian Bossuet, Guy Gogniat, Jean-Philippe Diguet and Jean-Luc Philippe --
Ch. 5. Design Techniques --
The Syslib-Picasso Methodology for the Co-Design Specification Capture Phrase / Luc Filion, Jerome Chevalier, Guy Bois and El Mostapha Aboulhamid --
Automatic Porting Of Binary File Descriptor Library / Maghsoud Abbaspour and Jianwen Zhu --
Code Compression on Transport Triggered Architectures / Jari Heikkinen, Jarmo Takala and Jaakko Sertamo --
An Approach To Flexible Multi-Level Network Design / V. Cheushev, J. Kolodziejczyk, T. Luba, C. Moraga, P. Sapiecha, V. Shmerko and S. Yanushkevich --
Ch. 6. Memory --
Survey of Emerging Nonvolatile Embedded Memory Technologies / Bruce F. Cockburn --
Configurable Parallel Memory Implementation For System-on-Chip Designs / Jarno Vanne, Eero Aho, Kimmo Kuusilinna and Tomo Hamalainen --
XOR-scheme Implementations In Configurable Parallel Memory / Eero Aho, Jarno Vanne, Kimmo Kuusilinna and Timo Hamalainen --
A Novel Low Power Embedded Memory Architecture for MPEG-4 Applications with Mobile Devices / Mohammed Sayed and Wael Badawy --
Assessment of MPEG-4 VTC and JPEG2000 Dynamic Memory Requirements / Gauthier Lafruit and Jan Bormans --
Ch. 7. Circuit Techniques --
Modified Distributed Arithmetic Architecture for Adiabatic DSP Systems / Dusan Suvakovic and C. Andre T. Salama --
Design of a CMOS Wide Range Logarithmic Amplifier with a Modified Parallel Architecture / Sanghoon Joo, Minkyu Song, Hyunyeon Cho and Sangki Kim --
Digital Hardware Implementation of Continuous & Discrete Chaotic Generators / Mohamed I. Sobhy, Mohammed A. Aseeri and Alaa E. R. Shehata --
Novel 1-Bit Full Adder Cells for Low-Power System-On-Chip Applications / Mohammed Sayed and Wael Badawy --
Ch. 8. Low Power --
A New Logic Method for Considering Low Power and High Testability / Yoon-Sik Son and Jong-Wha Chong --
System Synthesis for Optically-Connected, Multiprocessors On-chip / Neal K. Bambha and S. S. Bhattacharyya --
Low Power System On Chip Platform Architecture for High Performance Applications / W. C. Lo, A. T. Erdogan and T. Arslan --
Ch. 9. Interconnect and Technology --
SOC Interconnect in Deep Submicron / Magdy Bayoumi --
Optimizing Inductive Interconnect for Low Power / Magdy A. El-Moursy and Eby G. Friedman --
Skin Effects in System on a Chip Interconnects / Shizhong Mei and Yehea I. Ismail --
Ch. 10. Micro Electro Mechanical Systems --
Road Map Towards Designing MEMS Devices with High-Reliability / Walied A. Moussa --
A MEMS Socket Interface For SoC Connectivity / Sazzadur Chowdhury, M. Ahmadi, G. A. Jullien and W. C. Miller --
On the Application of Finite Element to Investigate the Reliability of Electrostatic Comb-Drive Actuators Utilized in Micro-Fluidic and Space Systems / Hesham Ahmed, Walied Moussa and Wael Badawy --
An HDL Model For A Vacuum-Sealed Micromachined Pressure Sensor / Rafik S. Guindi --
Performance Analysis of MEMS-based Intertial Sensors for Positioning Applications / Walid Abdel-Hamid, Aboelmagd Noureldin, Naser El-Sheimy and Gerard Lachapellee.
Series Title: Kluwer international series in engineering and computer science, SECS 711.
Responsibility: edited by Wael Badawy, Graham Jullien.
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Primary Entity<\/h3>\n
<http:\/\/www.worldcat.org\/oclc\/50478525<\/a>> # System-on-chip for real-time applications<\/span>\n\u00A0\u00A0\u00A0\u00A0a \nschema:CreativeWork<\/a>, schema:Book<\/a> ;\u00A0\u00A0\u00A0\nlibrary:oclcnum<\/a> \"50478525<\/span>\" ;\u00A0\u00A0\u00A0\nlibrary:placeOfPublication<\/a> <http:\/\/id.loc.gov\/vocabulary\/countries\/mau<\/a>> ;\u00A0\u00A0\u00A0\nlibrary:placeOfPublication<\/a> <http:\/\/dbpedia.org\/resource\/Boston<\/a>> ; # Boston<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/id.loc.gov\/authorities\/subjects\/sh2009115143<\/a>> ; # Application-specific integrated circuits--Design and construction<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/id.worldcat.org\/fast\/811723<\/a>> ; # Application-specific integrated circuits--Design and construction<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/id.worldcat.org\/fast\/1141473<\/a>> ; # Systems on a chip<\/span>\n\u00A0\u00A0\u00A0\nschema:about<\/a> <http:\/\/dewey.info\/class\/621.395\/e21\/<\/a>> ;\u00A0\u00A0\u00A0\nschema:bookFormat<\/a> bgn:PrintBook<\/a> ;\u00A0\u00A0\u00A0\nschema:contributor<\/a> <http:\/\/viaf.org\/viaf\/46636411<\/a>> ; # Graham Jullien<\/span>\n\u00A0\u00A0\u00A0\nschema:contributor<\/a> <http:\/\/viaf.org\/viaf\/1839124<\/a>> ; # Wael Badawy<\/span>\n\u00A0\u00A0\u00A0\nschema:datePublished<\/a> \"2003<\/span>\" ;\u00A0\u00A0\u00A0\nschema:description<\/a> \"Ch. 1. Introduction -- System on Chip: The Challenge and Opportunities \/ Wael Badawy -- Electronic Product Innovation Direct Mapped Signal Processing SoC Cores \/ John V. McCanny -- System-On-Chip Implementation of Signal Processors \/ Earl E. Swartzlander, Jr. -- Ch. 2. Design Reuse -- Methodologies and Strategies for Effective Design-Reuse \/ Ludovic Loiseau and Yvon Savaria -- A VHDL\/SystemC Comparison in Handling Design Reuse \/ Luc Charest and El Mostapha Aboulhamid -- Aspect Partitioning for Hardware Verification Reuse \/ Sebastien Regimbal, Jean-FrancoisLemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid and Andre Baron -- Reconfigurable Combinatorial Accelerators for Real Time Processing \/ I. Skliarova and A. B. Ferrari -- Tuning Methodologies for Parameterized Systems Design \/ Guiseppe Ascia, Vincenzo Catania and Maurizio Palesi -- Ch. 3. Test and Verification -- Formal Verifications of Systems on Chips: Current and Future Directions \/ Khaled M. Elleithy -- A Practical Approach to the Formal Verification of SoC\'s with Symbolic Model-Checking \/ Emil Dumitrescu -- High Performance Verification Solutions for SOC Designs \/ Makarand Joshi and Ashok Kumar -- Novel Test Methodologies for SoC\/IP Design: Implementation and Comparison \/ L. Hong, M. Nahvi, R. Fung, A. Ivanov and R. Saleh -- Ch. 4. Modeling -- SOC Modeling and Simulation Based on Java \/ Henry Fu and Richard F. Hobson -- RTOS Modeling Using SystemC \/ Mohamed Abd El-Salam, Ashraf Salem and Gamal Aly -- Modeling, Synthesis and Implementation of Communicating Hierarchical FSM \/ Valery Sklyarov -- A Modeling Method for Reconfigurable Architectures \/ Lilian Bossuet, Guy Gogniat, Jean-Philippe Diguet and Jean-Luc Philippe -- Ch. 5. Design Techniques -- The Syslib-Picasso Methodology for the Co-Design Specification Capture Phrase \/ Luc Filion, Jerome Chevalier, Guy Bois and El Mostapha Aboulhamid -- Automatic Porting Of Binary File Descriptor Library \/ Maghsoud Abbaspour and Jianwen Zhu -- Code Compression on Transport Triggered Architectures \/ Jari Heikkinen, Jarmo Takala and Jaakko Sertamo -- An Approach To Flexible Multi-Level Network Design \/ V. Cheushev, J. Kolodziejczyk, T. Luba, C. Moraga, P. Sapiecha, V. Shmerko and S. Yanushkevich -- Ch. 6. Memory -- Survey of Emerging Nonvolatile Embedded Memory Technologies \/ Bruce F. Cockburn -- Configurable Parallel Memory Implementation For System-on-Chip Designs \/ Jarno Vanne, Eero Aho, Kimmo Kuusilinna and Tomo Hamalainen -- XOR-scheme Implementations In Configurable Parallel Memory \/ Eero Aho, Jarno Vanne, Kimmo Kuusilinna and Timo Hamalainen -- A Novel Low Power Embedded Memory Architecture for MPEG-4 Applications with Mobile Devices \/ Mohammed Sayed and Wael Badawy -- Assessment of MPEG-4 VTC and JPEG2000 Dynamic Memory Requirements \/ Gauthier Lafruit and Jan Bormans -- Ch. 7. Circuit Techniques -- Modified Distributed Arithmetic Architecture for Adiabatic DSP Systems \/ Dusan Suvakovic and C. Andre T. Salama -- Design of a CMOS Wide Range Logarithmic Amplifier with a Modified Parallel Architecture \/ Sanghoon Joo, Minkyu Song, Hyunyeon Cho and Sangki Kim -- Digital Hardware Implementation of Continuous & Discrete Chaotic Generators \/ Mohamed I. Sobhy, Mohammed A. Aseeri and Alaa E. R. Shehata -- Novel 1-Bit Full Adder Cells for Low-Power System-On-Chip Applications \/ Mohammed Sayed and Wael Badawy -- Ch. 8. Low Power -- A New Logic Method for Considering Low Power and High Testability \/ Yoon-Sik Son and Jong-Wha Chong -- System Synthesis for Optically-Connected, Multiprocessors On-chip \/ Neal K. Bambha and S. S. Bhattacharyya -- Low Power System On Chip Platform Architecture for High Performance Applications \/ W. C. Lo, A. T. Erdogan and T. Arslan -- Ch. 9. Interconnect and Technology -- SOC Interconnect in Deep Submicron \/ Magdy Bayoumi -- Optimizing Inductive Interconnect for Low Power \/ Magdy A. El-Moursy and Eby G. Friedman -- Skin Effects in System on a Chip Interconnects \/ Shizhong Mei and Yehea I. Ismail -- Ch. 10. Micro Electro Mechanical Systems -- Road Map Towards Designing MEMS Devices with High-Reliability \/ Walied A. Moussa -- A MEMS Socket Interface For SoC Connectivity \/ Sazzadur Chowdhury, M. Ahmadi, G. A. Jullien and W. C. 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