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System-on-chip test architectures : nanometer design for testability

Author: Laung-Terng Wang; Charles E Stroud; Nur A Touba
Publisher: Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008.
Series: Morgan Kaufmann series in systems on silicon.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and  Read more...

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Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Laung-Terng Wang; Charles E Stroud; Nur A Touba
ISBN: 9780123739735 012373973X
OCLC Number: 140109577
Description: xxxvi, 856 pages : illustrations ; 25 cm.
Contents: Cover --
Title page --
Copyright Page --
Table of Contents --
Preface --
In the Classroom --
Acknowledgments --
Contributors --
About the Editors --
Chapter 1 Introduction --
1.1 Importance of System-on-Chip Testing --
1.1.1 Yield and Reject Rate --
1.1.2 Reliability and System Availability --
1.2 Basics of SOC Testing --
1.2.1 Boundary Scan (IEEE 1149.1 Standard) --
1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard) --
1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687) --
1.2.4 Core-Based Testing (IEEE 1500 Standard) --
1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard) --
1.3 Basics of Memory Testing --
1.4 SOC Design Examples --
1.4.1 BioMEMS Sensor --
1.4.2 Network-on-Chip Processor --
1.5 About This Book --
1.5.1 DFT Architectures --
1.5.2 New Fault Models and Advanced Techniques --
1.5.3 Yield and Reliability Enhancement --
1.5.4 Nanotechnology Testing Aspects --
1.6 Exercises --
Acknowledgments --
References --
Chapter 2 Digital Test Architectures --
2.1 Introduction --
2.2 Scan Design --
2.2.1 Scan Architectures --
2.2.2 Low-Power Scan Architectures --
2.2.3 At-Speed Scan Architectures --
2.3 Logic Built-In Self-Test --
2.3.1 Logic BIST Architectures --
2.3.2 Coverage-Driven Logic BIST Architectures --
2.3.3 Low-Power Logic BIST Architectures --
2.3.4 At-Speed Logic BIST Architectures --
2.3.5 Industry Practices --
2.4 Test Compression --
2.4.1 Circuits for Test Stimulus Compression --
2.4.2 Circuits for Test Response Compaction --
2.4.3 Low-Power Test Compression Architectures --
2.4.4 Industry Practices --
2.5 Random-Access Scan Design --
2.5.1 Random-Access Scan Architectures --
2.5.2 Test Compression RAS Architectures --
2.5.3 At-Speed RAS Architectures --
2.6 Concluding Remarks --
2.7 Exercises --
Acknowledgments --
References --
Chapter 3 Fault-Tolerant Design --
3.1 Introduction --
3.2 Fundamentals of Fault Tolerance --
3.2.1 Reliability --
3.2.2 Mean Time to Failure (MTTF) --
3.2.3 Maintainability --
3.2.4 Availability --
3.3 Fundamentals of Coding Theory --
3.3.1 Linear Block Codes --
3.3.2 Unidirectional Codes --
3.3.3 Cyclic Codes --
3.4 Fault Tolerance Schemes --
3.4.1 Hardware Redundancy --
3.4.2 Time Redundancy --
3.4.3 Information Redundancy --
3.5 Industry Practices --
3.6 Concluding Remarks --
3.7 Exercises --
Acknowledgments --
References --
Chapter 4 System/Network-on-Chip Test Architectures --
4.1 Introduction --
4.2 System-on-Chip (SOC) Testing --
4.2.1 Modular Testing of SOCs --
4.2.2 Wrapper Design and Optimization --
4.2.3 TAM Design and Optimization --
4.2.4 Test Scheduling --
4.2.5 Modular Testing of Mixed-Signal SOCs --
4.2.6 Modular Testing of Hierarchical SOCs --
4.
Series Title: Morgan Kaufmann series in systems on silicon.
Responsibility: edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba.
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