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Wafer scale integration : proceedings of a workshop held in Southampton from 10 July to 12 July 1985

Author: C R Jesshope; Will Moore
Publisher: Bristol : Hilger, ©1986.
Edition/Format:   Print book : Conference publication : EnglishView all editions and formats
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Additional Physical Format: Online version:
Wafer scale integration.
Bristol : Hilger, ©1986
(OCoLC)568211905
Material Type: Conference publication
Document Type: Book
All Authors / Contributors: C R Jesshope; Will Moore
ISBN: 0852744978 9780852744970
OCLC Number: 13361746
Description: xii, 274 pages : illustrations ; 24 cm
Contents: A critical review of fault-tolerant chips and WSI: General problems: Graph-theoretic approaches to fault-tolerant WSI processor arrays. An analysis of the interconnection problem for WSI. Wafer scale integration using discretionary micro-transmission line interconnections. A power distribution stategy for WSI. Clock distribution techniques for WSI. Interconnection strategies: Redundancy strategies for WSI. Interconnection strategies for the WASP device. A programmable switch matrix for the wafer scale integration of a processor array. Wafer scale integration based on self-organisation. fault-tolerant wafer scale architectures using large crossbar switch arrays. Automatic partitioning for yeild enhancement. Architectures: WASP - a WSI associative string processor for structured data processing. The reconfigurable processor array - an architecture in need of WSI. Reduction on a wafer. COBWEB - a reduction architecture. A WSI system for the computation of the two-dimensional fast Fourier transform. The implementation of a two-dimensional redundancy scheme in a wafer scale high-speed disk memory. Restructurable very large scale integration: The RVLSI approach to wafer scale integration. Laser-linking technology for RVSLI. Computer aided design and testing for RVLSI. Applications of RVLSI to signal processing. Testability: A test method for a parameterised cell disign approach to fault-tolerant VLSI and wafer scale integration. Token-triggered systolic diagnosis of wafer scale arrays. Fault tolerance in a large bit-level systolic array.
Responsibility: edited by Chris Jesshope, Will Moore.

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